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Mar 12, 2015
08:33 AM
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Mar 12, 2015
08:33 AM
Hi!
I'm trying to get my USIC to work as SPI Master, however in the datasheets I couldn't find a good guide to make it work. I'm not using the DAVE-RTOS code generator, I'm working in native-C. So far I tried to take the demo code and see how UART is initialized and tryed to make it for SPI but no luck so far.
Any help is appreciated!
I'm trying to get my USIC to work as SPI Master, however in the datasheets I couldn't find a good guide to make it work. I'm not using the DAVE-RTOS code generator, I'm working in native-C. So far I tried to take the demo code and see how UART is initialized and tryed to make it for SPI but no luck so far.
void initSPI(void) {
/* SPI Master initialization */
uint32_t spiFdrStep = 0, spiFsclk = 500000;
uint8_t spiBrgPdiv = 0;
/* if PPPEN = 0
* fsclk = fsys x STEP/1024 x 1/2 x 1/PDIV+1
*
* if PPPEN = 1
* fsclk = fsys x 1/2 x STEP/1024 x 1/2 x 1/PDIV+1
*/
/* Calculate settings for desired fsclk, PPPEN = 1 */
while(1) {
spiFdrStep = (spiFsclk * 1024 * 2 * 2 * (spiBrgPdiv+1)) / SystemCoreClock;
if(!((0 <= spiFdrStep) && (spiFdrStep < 1024))) {
spiBrgPdiv++;
} else {
break;
}
}
/* Disable clock gating to USIC0 */
SCU_GENERAL->PASSWD = 0x000000C0UL; /* disable bit protection */
SCU_CLK->CGATCLR0 |= SCU_CLK_CGATCLR0_USIC0_Msk;
SCU_GENERAL->PASSWD = 0x000000C3UL; /* enable bit protection */
/* Enable the module kernel clock and the module functionality */
USIC0_CH0->KSCFG |= (1ul << USIC_CH_KSCFG_MODEN_Pos)
| (1ul << USIC_CH_KSCFG_BPMODEN_Pos);
/* Set P0.15 as Input, MISO */
PORT0->IOCR12 = (INPUT << PORTn_IOCR12_PC15_Pos);
USIC0_CH0->DX0CR |= (1ul << USIC_CH_DX0CR_DSEL_Pos) /* Select DX0B */
| (1ul << USIC_CH_DX0CR_INSW_Pos);
/* Set P0.14 as Onput, MOSI */
PORT0->IOCR12 |= (OUTPUT_PP_AF6 << PORTn_IOCR12_PC14_Pos);
/* Set P0.7 as Output, SCLK */
PORT0->IOCR4 |= (OUTPUT_PP_AF6 << PORTn_IOCR4_PC7_Pos);
/* Set P0.9 as Output, SELECT */
PORT0->IOCR8 |= (OUTPUT_PP_AF6 << PORTn_IOCR8_PC9_Pos);
/* Configuration of Channel Control Register, set USIC to SSC.SPI */
USIC0_CH0->CCR |= (1ul << USIC_CH_CCR_MODE_Pos);
/* Configure Fractional Divider Register */
USIC0_CH0->FDR |= (spiFdrStep << USIC_CH_FDR_STEP_Pos)
| (3ul << USIC_CH_FDR_DM_Pos);
/* Configure Baud Rate Generator Register */
USIC0_CH0->BRG |= (1ul << USIC_CH_BRG_PPPEN_Pos)
| (spiBrgPdiv << USIC_CH_BRG_PDIV_Pos)
| (0ul << USIC_CH_BRG_PCTQ_Pos)
| (9ul << USIC_CH_BRG_DCTQ_Pos);
USIC0_CH0->PCR_SSCMode |= (1ul << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /* Enables/disables the generation of the master slave select signal */
| (1ul << USIC_CH_PCR_SSCMode_SELINV_Pos) /* Active low for CS */
| (1ul << USIC_CH_PCR_SSCMode_SELCTR_Pos) /* Direct select */
| (1ul << USIC_CH_PCR_SSCMode_SELO_Pos) /* Activate SELO */
| (1ul << USIC_CH_PCR_SSCMode_MCLK_Pos); /* Master Clock Enable */
/* Configure Shift Control Register */
USIC0_CH0->SCTR |= (1ul << USIC_CH_SCTR_SDIR_Pos) /* Shift out MSB first */
| (0ul << USIC_CH_SCTR_DSM_Pos) /* Data Shift Mode */
| (0ul << USIC_CH_SCTR_TRM_Pos) /* Transmission Mode */
| (15ul << USIC_CH_SCTR_FLE_Pos) /* Frame Length */
| (15ul << USIC_CH_SCTR_WLE_Pos); /* Word Length */
/* Configure Transmission Control Status */
USIC0_CH0->TCSR |= (1ul << USIC_CH_TCSR_FLEMD_Pos) /* FLE Mode */
| (1ul << USIC_CH_TCSR_WLEMD_Pos) /* WLE Mode */
| (1ul << USIC_CH_TCSR_SELMD_Pos) /* Select Mode */
| (1ul << USIC_CH_TCSR_SOF_Pos) /* Start Of Frame */
| (1ul << USIC_CH_TCSR_EOF_Pos) /* End Of Frame */
| (1ul << USIC_CH_TCSR_TDV_Pos) /* Transmit Data Valid */
| (1ul << USIC_CH_TCSR_TDSSM_Pos) /* TBUF Data Single Shot Mode */
| (1ul << USIC_CH_TCSR_TDEN_Pos); /* TBUF Data Enable */
/* Configure Transmit Buffer */
/* Standard transmit buffer event is enabled */
/* Define start entry of Transmit Data FIFO buffer DPTR = 0*/
USIC0_CH0->TBCTR &= ~(USIC_CH_TBCTR_SIZE_Msk | USIC_CH_TBCTR_DPTR_Msk);
/* Set Transmit Data Buffer to 32 and set data pointer to position 0*/
USIC0_CH0->TBCTR |= ((0x05 << USIC_CH_TBCTR_SIZE_Pos)|(0x00 << USIC_CH_TBCTR_DPTR_Pos));
}
Any help is appreciated!
3 Replies
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Mar 12, 2015
10:43 PM
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Mar 12, 2015
10:43 PM
Hi,
There are some available sample non-app codes on SPI that you can reference from the link below. These are for XMC1200 but I understand for SPI, the code should be device independent.
http://www.infineon.com/cms/en/product/evaluation-boards/KIT_XMC12_BOOT_001/productType.html?product...
Looking at your code, I see a few instances that may cause problem:
- FDR.DM = 3 disables the fractional divider. It should be either 1 (normal divider mode) or 2 (fractional divider mode)
- PCR_SSCmode.SELO = 1 selects the signal SELO1. But you need P0.9 which is signal SELO0. To select SELO0, the bit field should be programmed to 0
- SCTR.TRM = 0 will not work. TRM needs to be programmed to 1 for SPI.
- Besides TCSR.TDEN and TCSR.TDSSM, I would suggest to program all other TCSR bit fields to 0 for now.
Hope this helps.
There are some available sample non-app codes on SPI that you can reference from the link below. These are for XMC1200 but I understand for SPI, the code should be device independent.
http://www.infineon.com/cms/en/product/evaluation-boards/KIT_XMC12_BOOT_001/productType.html?product...
Looking at your code, I see a few instances that may cause problem:
- FDR.DM = 3 disables the fractional divider. It should be either 1 (normal divider mode) or 2 (fractional divider mode)
- PCR_SSCmode.SELO = 1 selects the signal SELO1. But you need P0.9 which is signal SELO0. To select SELO0, the bit field should be programmed to 0
- SCTR.TRM = 0 will not work. TRM needs to be programmed to 1 for SPI.
- Besides TCSR.TDEN and TCSR.TDSSM, I would suggest to program all other TCSR bit fields to 0 for now.
Hope this helps.
Not applicable
Mar 13, 2015
10:46 AM
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Mar 13, 2015
10:46 AM
Thank You! It's working now!
Not applicable
Jun 02, 2015
12:24 AM
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Jun 02, 2015
12:24 AM
hello!Can you help me to use the spi,thanks.Is there some demo codes?
Stormrage wrote:
Thank You! It's working now!