Cache invalidation

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cross mob
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Hi all,
I'm working on AURIX TC277TU architecture and I'm not able to find how to invalidate CPUs data caches.

TC277TU has two different processors: TC1.6P and TC1.6E. TC1.6E has not data cache but uses a buffer.

Is it possible to invalidate (clear) all caches and buffer during run-time execution?

Thanks to everybody,
best greetings!

----------------------------
Italo
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7 Replies
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I found that is possible to invalidate every single cache line by using one of the following instructions:
* CACHEA.I
* CACHEA.W
I didn't find anything about full cache lines invalidation.

Now the question is: which is CACHEA.I and CACHEA.W syntax?
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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received
Try this instead:

// invalidate all data caches
OVCCON.U = 0x00040007; // DCINVAL = 1, CSEL2=1, CSEL1=1, CSEL0=1

// invalidate program cache
PCON1.B.PCINV = 1;

// invalidate program line buffer
PCON1.B.PBINV = 1;
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Not applicable
These registers are write protected?

How can I disable the protection to write on OVCCON register?
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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received
By default, the CPU is in supervisor mode (PSW.IO=2), and OVCCON access is enabled (SCU_ACCEN0 = 0xFFFFFFFF). If you're in user mode (PSW.IO=0 or 1), or SCU_ACCEN0 has been changed, you'll need to change that before you can write to OVCCON.
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User18223
Level 1
Level 1
Hello,

I want to invalidate Program cache. i used the suggested instruction :

// invalidate program cache
PCON1.B.PCINV = 1;

But that generates a Trap (Trap_instructionError) and the CPU enter into Debug State.
I'm working with a TC275 (a shieldBuddy).

Any suggestion please ?
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cwunder
Employee
Employee
5 likes given 50 likes received 50 solutions authored
PCON1 is a Core Special Function Registers (CSFR)
__mtcr(CPU_PCON1, 1);
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User18223
Level 1
Level 1
Thank you cwunder.
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