Banner_AURIX_Security-Solution Banner_AURIX_Safety_Products ShieldBuddy TC275 Banner_AURIX_OnzerOS Banner_AURIX_DevelopmentStudio


+ Reply to Thread
Results 1 to 7 of 7

Thread: Cache invalidation

  1. #1
    Italo
    Guest

    Cache invalidation

    Hi all,
    I'm working on AURIX TC277TU architecture and I'm not able to find how to invalidate CPUs data caches.

    TC277TU has two different processors: TC1.6P and TC1.6E. TC1.6E has not data cache but uses a buffer.

    Is it possible to invalidate (clear) all caches and buffer during run-time execution?

    Thanks to everybody,
    best greetings!

    ----------------------------
    Italo
    Last edited by Italo; Jan 23rd, 2015 at 01:41 AM.

  2. #2
    Italo
    Guest
    I found that is possible to invalidate every single cache line by using one of the following instructions:
    * CACHEA.I
    * CACHEA.W
    I didn't find anything about full cache lines invalidation.

    Now the question is: which is CACHEA.I and CACHEA.W syntax?

  3. #3

    Infineon Employee
    Infineon Employee
    Neal Manson is on a distinguished road
    Join Date
    May 2014
    Location
    Livonia, MI
    Posts
    37
    Points
    81.875
    Try this instead:

    // invalidate all data caches
    OVCCON.U = 0x00040007; // DCINVAL = 1, CSEL2=1, CSEL1=1, CSEL0=1

    // invalidate program cache
    PCON1.B.PCINV = 1;

    // invalidate program line buffer
    PCON1.B.PBINV = 1;
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  4. #4
    acornagl
    Guest
    These registers are write protected?

    How can I disable the protection to write on OVCCON register?

  5. #5

    Infineon Employee
    Infineon Employee
    Neal Manson is on a distinguished road
    Join Date
    May 2014
    Location
    Livonia, MI
    Posts
    37
    Points
    81.875
    By default, the CPU is in supervisor mode (PSW.IO=2), and OVCCON access is enabled (SCU_ACCEN0 = 0xFFFFFFFF). If you're in user mode (PSW.IO=0 or 1), or SCU_ACCEN0 has been changed, you'll need to change that before you can write to OVCCON.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  6. #6
    New Member New Member amarir is on a distinguished road
    Join Date
    Oct 2019
    Posts
    1
    Points
    40
    Hello,

    I want to invalidate Program cache. i used the suggested instruction :

    // invalidate program cache
    PCON1.B.PCINV = 1;

    But that generates a Trap (Trap_instructionError) and the CPU enter into Debug State.
    I'm working with a TC275 (a shieldBuddy).

    Any suggestion please ?
    Last edited by amarir; Feb 13th, 2020 at 08:32 AM.

  7. #7
    Advanced Advanced cwunder is on a distinguished road
    Join Date
    Feb 2015
    Location
    USA
    Posts
    153
    Points
    2997.5
    PCON1 is a Core Special Function Registers (CSFR)
    Code:
    __mtcr(CPU_PCON1, 1);

+ Reply to Thread
Disclaimer

All content and materials on this site are provided “as is“. Infineon makes no warranties or representations with regard to this content and these materials of any kind, whether express or implied, including without limitation, warranties or representations of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, whether express or implied, is granted by Infineon. Use of the information on this site may require a license from a third party, or a license from Infineon.


Infineon accepts no liability for the content and materials on this site being accurate, complete or up- to-date or for the contents of external links. Infineon distances itself expressly from the contents of the linked pages, over the structure of which Infineon has no control.


Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Usage Terms of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Usage Terms of this site. Infineon reserves the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.