SPI with no trailing delay?

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Hi everybody,

SPI App only allows a minimum trailing delay of 1 SCLK Period. However I want my chip select signal to go inactive with the last transmitted data bit ( respectively the last edge of the clock).
So any clues on how to do so?
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Hi,

In standard SSC applications, the trailing delay is mainly used to ensure stability on the output lines as well as to respect the slave hold time requirements.
Do you mean that you don't want any hold time? I'm afraid it is not possible.

Best regards,
Sophia
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Thanks for your reply Sophia, seems like you didn´t get me right.
Yes I need hold time, but I want the slave select signal (called Update below) to be already high with the last edge of clock.

That´s how my protocol should look like:
1025.attach

That´s what I measered with the Oscilloscope:
1026.attach

Best regards
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Hi,

It seems that your protocol is not a standard SSC protocol which is not supported by our USIC module.

Best regards,
Sophia
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