infineon4engineers

# Thread: Baudrate from f(sys)

1. ## Baudrate from f(sys)

Sorry for 'elementary' question, but I am stuck...

How can I calulate and load FDRL, BRGL, BRGH registers if I need exact baudrate?
E.g. I need 115200 baudrate, I have 80 MHz of f(sys), how may I calculate necessary FDRL coefficient and valuate necessity of next dividers?
Is there any formula to link baudrate and herz?

2. Hi elusive,

I would suggest you use DAVE2 to generate the code for USIC baudrate. It would be much easier.
Of course, if you insist of calculating the baud rate manually, you can look into the User Manual and look for the baud rate equation of each protocol.

3. Originally Posted by Jackson
Hi elusive,

I would suggest you use DAVE2 to generate the code for USIC baudrate. It would be much easier.
Of course, if you insist of calculating the baud rate manually, you can look into the User Manual and look for the baud rate equation of each protocol.
The thing was about how many herz should we offer and at which point to say that 'it is 19200 baudrate'.
I sorted out that 19200 baudrate == 19200 herz at 'Protocol Pre-Processor' stage.
DAVE is not used here. A special interface-like layer was developed to set new baudrates or other parameters easily in the proccess without recompilation. For example if you need to change baudrate after some conditions and restore to the 'default'.

4. I use the XMC1100 and use the following functions to set clock and bitrate:

void Init_SCU_CLK(void)
{
//--- SCU_CLK ----
SCU_GENERAL->PASSWD = 0xC0;
while(((SCU_GENERAL->PASSWD) & 2)){;} //wait until write enabled
SCU_CLK->CLKCR= (0x3ff<<20)+(1<<16)+(0<<8)+(0);//IDIV = 0 FDIV= 0 PCKLSEL= 1

SCU_GENERAL->PASSWD = 0xC3;
}

void Baudrategenerator (uint32_t Channel, uint32_t Protokoll, uint32_t Bitrate)
{ USIC_CH_TypeDef* USIC0_Chy=USIC0_CH0;//choose channel
if (Channel==1)USIC0_Chy=USIC0_CH1;
#define dco_dclk 64000000
double MCLK;
uint32_t IDIV=(SCU_CLK->CLKCR>>8)& 0xFF;
uint32_t FDIV=SCU_CLK->CLKCR & 0xFF;
if (IDIV==0) MCLK=32000000; // MCLK=dco_dclk/(PCLKSEL+1);
else MCLK=dco_dclk/(2*(IDIV+FDIV/256));

//--- Find STEP and PDIV from Bitrate ----
uint32_t DCTQ=9; //required for ASC, see datasheet
if (Protokoll==1) DCTQ=1; //for ASC: according datasheet DCTQ=0. With DCTQ=1 bitrate is correct
#define PCTQ 0
double F=1024*Bitrate/MCLK*(DCTQ+1)*(PCTQ+1);
double PDIV_1023=1023/F-1, PDIV_1022=1022/F-1;
uint32_t FDR_STEP=1023-(int)((PDIV_1023-(int)(PDIV_1023))/(PDIV_1023-PDIV_1022)+0.5); //+0.5 for rounding number
uint32_t PDIV=(int)(FDR_STEP/F-1+0.5);//+0.5 for rounding

USIC0_Chy->FDR = (0x2<<14)|FDR_STEP; //DM=2; Fractional Divider Mode selected

#define CLKSEL 0 //fractional divider frequency fFDselected
USIC0_Chy->BRG |= CLKSEL+(PCTQ<<8)+(DCTQ<<10)+(PDIV<<16);;
// ^^^^^^^^^ Bitrategenerator ^^^^^^^^^
}