Thank you Jackson
These are the changes i made please check.
#include //SFR declarations of the selected device
//#include
#include "GPIO.h"
/*******************************************************************************
** Macro Definitions **
*******************************************************************************/
#define CALIB00 0x480340E0
#define CALIB01 0x480340E4
/*******************************************************************************
** Private Variable Definitions **
*******************************************************************************/
uint32_t * SHS0_CALOC0 = (uint32_t *) CALIB00;
uint32_t * SHS0_CALOC1 = (uint32_t *) CALIB01;
/*******************************************************************************
** Function Declarations **
*******************************************************************************/
void delay (uint32_t delay);
void VADC_Init();
void ADC_SU_Calibration (void);
void ADC_PG_Calibration (void);
/*******************************************************************************
** Global Variable Definitions **
*******************************************************************************/
uint32_t ADC_Result[101]={0};
uint32_t i=0, j=0;
uint32_t result_sum=0;
uint32_t flag_condition1=0;
uint32_t flag_condition2=0;
uint32_t Init_Conv_Comp_flag = 0;
int main(void)
{
SCU_GENERAL->PASSWD = 0x000000C0UL; // disable bit protection
SCU_CLK->CLKCR = 0x3ff10200UL; // 32 MHz MCLK, 64 MHz PCLK
while((SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk));
SCU_GENERAL->PASSWD = 0x000000C3UL; // enable bit protection
P0_5_set_mode(OUTPUT_PP_GP); // pin set up p0.5 for relay2
P0_6_set_mode(OUTPUT_PP_GP); //pin setup p0.6 for relay1
/* Relay1 on for power on condition*/
P0_5_set(); //Relay2 off
P0_6_reset(); //Relay1 on
delay(1000);
// Initialize ADC
VADC_Init();
// Generate load event to start conversion
VADC->BRSMR |= (1 << VADC_BRSMR_LDEV_Pos & VADC_BRSMR_LDEV_Msk);
while(1)
{
if(Init_Conv_Comp_flag == 1)
{
/*threshold voltage 2v*/
if(result_sum<=1638)
{
if (flag_condition2==1)
{
delay(1000);
flag_condition1=1;
flag_condition2=0;
}
//flag_condition1=1;
/*Relay1 on <1032 count*/
P0_5_reset(); //Relay2 off
P0_6_set(); //Relay1 on
//Init_Conv_Comp_flag = 1;
}
else if (result_sum >1638)
{
if (flag_condition1==1)
{
delay(1000);
flag_condition1=0;
flag_condition2=1;
}
//flag_condition2=1;
/*Relay2 on >1032 count*/
P0_6_reset(); //Relay1 off
P0_5_set(); //Relay2 on
//Init_Conv_Comp_flag = 0;
} //end of else part
WR_REG(VADC->BRSMR, VADC_BRSMR_ENGT_Msk, VADC_BRSMR_ENGT_Pos, 1); //gating enabled
//Init_Conv_Comp_flag = 0;
} //end of con_Comp_flag
} //end of while
return 0;
} // end of main
void VADC0_C0_1_IRQHandler(void)
{
static int result_temp = 0;
ADC_Result=VADC->GLOBRES&0xFFF;
//result_sum += ADC_Result;
result_temp = ADC_Result+result_temp;
if(i==100)
{
result_sum = result_temp/100;
//result_sum = result_sum/100;
i=0;
result_temp=0;
Init_Conv_Comp_flag = 1;
WR_REG(VADC->BRSMR, VADC_BRSMR_ENGT_Msk, VADC_BRSMR_ENGT_Pos, 0); // Diable gating
//Init_Conv_Comp_flag = 0;
}
else{i++;}
//Init_Conv_Comp_flag = 1;
// Clear offset calibration values
*SHS0_CALOC0 = 0x8000;
*SHS0_CALOC1 = 0x8000;
}
void VADC_Init()
{
// Disable clock gating to VADC
SCU_GENERAL->PASSWD = 0x000000C0U; // Disable bit protection
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_VADC_Pos); // Disables clock gating for VADC kernel
while (SCU_CLK->CLKCR & (SCU_CLK_CLKCR_VDDC2LOW_Msk)); // Wait for the VDDC to stable
SCU_GENERAL->PASSWD = 0x000000C3UL; // Enable bit protection
//GLOBAL VADC INITIALIZATION
VADC->CLC = (0 << VADC_CLC_DISR_Pos & VADC_CLC_DISR_Msk) | // On request: enable the module clock
(0 << VADC_CLC_DISS_Pos & VADC_CLC_DISS_Msk) | // Module clock is enabled
(0 << VADC_CLC_EDIS_Pos & VADC_CLC_EDIS_Msk); // Sleep mode request is enabled and functional
while(VADC->CLC!=0); // wait for module clock enabled
// Converter ON
SHS0->SHSCFG = (0 << SHS_SHSCFG_ANOFF_Pos & SHS_SHSCFG_ANOFF_Msk)|SHS_SHSCFG_SCWC_Msk;
*(uint32_t *)0x40010500 = 0X0001; //Errata ADC_AI.003
// Wait until analog converter is on (SHSCFG.ANRDY = 1)
while (!(SHS0->SHSCFG & SHS_SHSCFG_ANRDY_Msk)) ;
delay(12); // Added ~15usec wait time for ADC power to stable
// Trigger Start Up calibration
ADC_SU_Calibration();
// Trigger gain calibration
ADC_PG_Calibration(); //do not modify DPCAL and SUCAL bitfields form GLOBCFG from here onwards to avoid wrong calibration configurations
// Background source configuration (include 1 channel -ch 7 group 0 w/o auto scan (continuous conversions).
VADC->BRSSEL[0] = (1 << VADC_BRSSEL_CHSELG7_Pos & VADC_BRSSEL_CHSELG7_Msk);
VADC->BRSMR = (1 << VADC_BRSMR_ENGT_Pos & VADC_BRSMR_ENGT_Msk)| //Enable gating always
(1 << VADC_BRSMR_SCAN_Pos & VADC_BRSMR_SCAN_Msk); //Enable autoscan
// Enable interrupt for global result register
VADC->GLOBRCR = (0x1 << VADC_GLOBRCR_SRGEN_Pos & VADC_GLOBRCR_SRGEN_Msk);
// Route event trigger to service request line (interrupt node)
VADC->GLOBEVNP = (0x1 << VADC_GLOBEVNP_REV0NP_Pos & VADC_GLOBEVNP_REV0NP_Msk);
// Enable nvic node for SR1
NVIC_EnableIRQ(VADC0_C0_1_IRQn);
}
// Startup calibration
void ADC_SU_Calibration (void)
{
uint16_t wait;
// Enable calibration
*SHS0_CALOC0 = 0x00;
*SHS0_CALOC1 = 0x00;
// Enable SU calibration ADC
VADC->GLOBCFG |= (1 << VADC_GLOBCFG_SUCAL_Pos & VADC_GLOBCFG_SUCAL_Msk)|
(1 << VADC_GLOBCFG_DPCAL0_Pos & VADC_GLOBCFG_DPCAL0_Msk);
// Wait for 1920cycles or 60us for the startup calibration to complete
wait = 20;
while(wait > 0)
{
wait--;
*SHS0_CALOC0 = 0x8000; // Clear offset calibration values
*SHS0_CALOC1 = 0x8000;
}
} // End of ADC_SU_Calibration
// Gain calibration routine
void ADC_PG_Calibration (void)
{
uint16_t i, j, adc_result_aux;
*(uint32_t *)0x480340BC = 0X3F100400; //Errata ADC_AI.004
VADC->BRSSEL[0] = (1 << VADC_BRSSEL_CHSELG0_Pos & VADC_BRSSEL_CHSELG0_Msk);//set G0_Ch0 for dummy conversions
// SUCAL=0, DPCAL0=0, DPCAL1=0 (DPCAL1 has to be kept to 0)
VADC->GLOBCFG |= 0x00;
*SHS0_CALOC0 = 0x8000; // Clear offset calibration values
*SHS0_CALOC1 = 0x8000;
// Trigger dummy conversions (9 x 2000 times)
for (i=0; i < 2000; i++)
{
for (j=0; j < 9; j++)
{
VADC->BRSMR |= (1 << VADC_BRSMR_ENGT_Pos & VADC_BRSMR_ENGT_Msk)| //Enable gating always
(0 << VADC_BRSMR_SCAN_Pos & VADC_BRSMR_SCAN_Msk)| //No autoscan-->only 1 conversion
(1 << VADC_BRSMR_LDEV_Pos & VADC_BRSMR_LDEV_Msk); //Generate a load event
// wait for valid result
while (!(VADC->GLOBRES & VADC_GLOBRES_VF_Msk));
//read result
adc_result_aux = (VADC->GLOBRES & VADC_GLOBRES_RESULT_Msk);
// Clear offset calibration values
*SHS0_CALOC0 = 0x8000;
*SHS0_CALOC1 = 0x8000;
}
}
// Redundant code to avoid warning
if(adc_result_aux == 0);
// Wait until last gain cal step is finished
while ( (SHS0->SHSCFG & SHS_SHSCFG_STATE_Msk) != 0 )
{
// Clear offset calibration values
*SHS0_CALOC0 = 0x8000;
*SHS0_CALOC1 = 0x8000;
}
VADC->GLOBCFG = 0x00; // Ensure Post-Calibration enable (SUCAL=0, DPCAL0=0, DPCAL1=0)
// Reset used register to reset value
VADC->GLOBRES = 0x00;
VADC->BRSMR = 0x00;
VADC->BRSSEL[0] = 0x00;
} // End of ADC_PG_Calibration
void delay (uint32_t delay)
{
while(delay > 0)
{
delay--;
}
} // End of delay
