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Nov 13, 2014
10:39 PM
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Nov 13, 2014
10:39 PM
There are 4 programmable priority levels for each interrupt node in XMC1000 device.
You can declare multiple interrupt node for the same priority level.
However, the interrupt node with the same priority level would not overwrite or interrupt each other.
So, if one interrupt has already started, the other interrupt with the same priority level gets triggered have to be wait.
In the Reference Manual, it is mentioned that each priority level has a step of 64.
This DOES NOT mean that there are another 64 sub level in each priority level.
Basically, the bit [5:0] is masked off and only bits [7:0] is used for register NVIC_IPRx.
This means writing any value from 0-63 = 00, 64-127 = 01, 128-191 = 10, 192 = 11.
The most convenient way to set the interrupt priority is using the CMSIS function NVIC_SetPriority (IRQn_t IRQn, uint32_t priority).
IRQn refers to the interrupt node number and priority refers to value from 0 - 3.
You can declare multiple interrupt node for the same priority level.
However, the interrupt node with the same priority level would not overwrite or interrupt each other.
So, if one interrupt has already started, the other interrupt with the same priority level gets triggered have to be wait.
In the Reference Manual, it is mentioned that each priority level has a step of 64.
This DOES NOT mean that there are another 64 sub level in each priority level.
Basically, the bit [5:0] is masked off and only bits [7:0] is used for register NVIC_IPRx.
This means writing any value from 0-63 = 00, 64-127 = 01, 128-191 = 10, 192 = 11.
The most convenient way to set the interrupt priority is using the CMSIS function NVIC_SetPriority (IRQn_t IRQn, uint32_t priority).
IRQn refers to the interrupt node number and priority refers to value from 0 - 3.
2 Replies
Jun 24, 2022
02:54 AM
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Jun 24, 2022
02:54 AM
Hi,
This is the implementation of __NVIC_SetPriority from core_cm0.h of CMSIS
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
Since the following definition apply always in core_cm0.h:
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
and this in the various XMC1x00.h:
#define __NVIC_PRIO_BITS 2
It seems actually that only the 2 LSB bit of priority variable are used inside NVIC->IP register.
Do I miss something?
Regards,
L
Jun 27, 2022
01:11 AM
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Jun 27, 2022
01:11 AM
Hi L,
Your understanding is right. The processor implements only bits[7:6] of each field, bits [5:0] read as zero and ignore writes. There is a typo in the original response.
Best Regards,
Vasanth