Jitter Problem on CCU40 with different SystemClock Speeds

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Hi,

I have a problem with jitter on the CCU40_0 timer. The Timer is configured for 100kHz and there are no prescalers.

CCU40_CC40->PRS = SystemCoreClock / 100000

On 96MHz and 120MHz there are no problems. If I go down to 80MHz,72MHz, 60MHz then I have a jitter 40-100Hz. I am using this timer for the DMA Handshake to copy data from a GPIO Port into memory. The Timer interrupt is directly connected to the DMA via the DLR.

Tested clock settings:


#if (CLOCK_FSYS == 60000000)
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 7
#define SCU_PLL_PDIV 0
#define SCU_PLL_NDIV 39
#endif

#if (CLOCK_FSYS == 72000000)
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 5
#define SCU_PLL_PDIV 0
#define SCU_PLL_NDIV 35
#endif

#if (CLOCK_FSYS == 80000000)
// #define SCU_PLL_K1DIV 1
// #define SCU_PLL_K2DIV 3
// #define SCU_PLL_PDIV 2
// #define SCU_PLL_NDIV 79

#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 5
#define SCU_PLL_PDIV 0
#define SCU_PLL_NDIV 39
#endif

// Values derated to 100MHz
#if (CLOCK_FSYS == 96000000)
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 4
#define SCU_PLL_PDIV 0
#define SCU_PLL_NDIV 39
#endif

// Values set to 120MHz
#if (CLOCK_FSYS == 120000000)
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 3
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
#endif


The clock settings are generated from Dave.

Can anybody tell me why the timer jitters more on lower system frequencies?

Regards

Thk
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3 Replies
Travis
Employee
Employee
First solution authored Welcome! 500 replies posted
Which device are u using?
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Not applicable
It is an XMC4500-F144K1024 AC EES (Infineon Hexagon Board)
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Not applicable
Hi thk,

Are you using internal clock?
100Hz of jitter in 100KHz is only 0.001%, is your application really critical about the jitter?
Recently we also received feedback about this but after investigate, this is due to how the internal oscillator works.
With the current design of the internal oscillator, this jitter is expected.
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