Sep 05, 2014
07:37 AM
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Sep 05, 2014
07:37 AM
//values calculated for 57.6 kbaud @ 8 MHz
#define FDR_STEP 590
#define BRG_PDIV 4
#define BRG_DCTQ 15
#define BRG_PCTQ 0
void SysTick_Handler(void) // 0.2s interrupt base
{
static uint8_t step = 0;
uint8_t i;
// const char Message1[] = "Visit www.infineon.com/XMC\r\n";
const char Message1[] = "UUUUUAUUUAUUUUUUUUAUUU/UUUAA"; //自己加上的
const char Message2[] = "Visit www.infineonforums.com\r\n\r\n";
P0_0_toggle();
if ((++step)==20) step = 0;
if (step==9) for(i=0; i<(sizeof(Message1)-1); i++) USIC0_CH1->IN[0] = Message1;
// if (step==19) for(i=0; i<(sizeof(Message2)-1); i++) USIC0_CH1->IN[0] = Message2;
}
void initUART(void)
{
//Kernel State Configuration Register - Module Enable + Bit Protection for MODEN
USIC0_CH1->KSCFG |= (1 << USIC_CH_KSCFG_MODEN_Pos) | (1 << USIC_CH_KSCFG_BPMODEN_Pos);
//Fractional divider mode selected
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_DM_Msk, USIC_CH_FDR_DM_Pos, 2);
//Step value
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_STEP_Msk, USIC_CH_FDR_STEP_Pos, FDR_STEP);
//PreDivider for CTQ, PCTQ = 0, Denominator for CTQ, DCTQ = 16
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PCTQ_Msk, USIC_CH_BRG_PCTQ_Pos, BRG_PCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_DCTQ_Msk, USIC_CH_BRG_DCTQ_Pos, BRG_DCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PDIV_Msk, USIC_CH_BRG_PDIV_Pos, BRG_PDIV);
//Configuration of USIC Shift Control
//Transmit/Receive LSB first is selected, Transmission Mode (TRM) = 1, Passive Data Level (PDL) = 1
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_PDL_Msk, USIC_CH_SCTR_PDL_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_TRM_Msk, USIC_CH_SCTR_TRM_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_SDIR_Msk, USIC_CH_SCTR_SDIR_Pos, 0); //自己加上的
//Set Word Length (WLE) & Frame Length (FLE)
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 7);
// WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 10); //自己加,经验证不可行
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_WLE_Msk, USIC_CH_SCTR_WLE_Pos, 7);
//Configuration of USIC Transmit Control/Status Register
//TBUF Data Enable (TDEN) = 1, TBUF Data Single Shot Mode (TDSSM) = 1
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDEN_Msk, USIC_CH_TCSR_TDEN_Pos, 1);
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDSSM_Msk, USIC_CH_TCSR_TDSSM_Pos, 1);
//Configuration of Protocol Control Register
//Sample Mode (SMD) = 1, 1 Stop bit is selected, Sample Point (SP) = 2, Pulse Length (PL) = 0
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SMD_Msk, USIC_CH_PCR_ASCMode_SMD_Pos, 1);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_STPB_Msk, USIC_CH_PCR_ASCMode_STPB_Pos, 0);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 9);
// WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 3); //自己加上的
//TBIF is set to simplify polling
WR_REG(USIC0_CH1->PSR_ASCMode, USIC_CH_PSR_TBIF_Msk, USIC_CH_PSR_TBIF_Pos, 1);
//Configuration of Transmitter Buffer Control Register
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_LIMIT_Msk, USIC_CH_TBCTR_LIMIT_Pos, 0);
//Configuration of Channel Control Register
//parity generation is disabled
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 2);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_PM_Msk, USIC_CH_CCR_PM_Pos, 0);
//Data Pointer & Buffer Size for Transmitter Buffer Control - DPTR = 64, SIZE = 6
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos, 0x06000040);
}
//----PIN-SETUP-------------------------------------------------------------------------------------
P0_0_set_mode(OUTPUT_PP_GP);
P1_2_set_mode(OUTPUT_PP_AF7);
P1_3_set_mode(INPUT);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
above are the related codes,the visual COM on computer displays "UUUUU_UUU_UUUUUUUU_UUUhUUU__",I select U because its ASCII is 01010101b whose 0 and 1 distribute evenly.The displayed codes on computer would be all wrong if I didn't select U as the member of array message1.It seems that the displayed codes on computer is the result of right shift one bit of one's complement of the members from array message1.
I don't know why and hope for some help.
#define FDR_STEP 590
#define BRG_PDIV 4
#define BRG_DCTQ 15
#define BRG_PCTQ 0
void SysTick_Handler(void) // 0.2s interrupt base
{
static uint8_t step = 0;
uint8_t i;
// const char Message1[] = "Visit www.infineon.com/XMC\r\n";
const char Message1[] = "UUUUUAUUUAUUUUUUUUAUUU/UUUAA"; //自己加上的
const char Message2[] = "Visit www.infineonforums.com\r\n\r\n";
P0_0_toggle();
if ((++step)==20) step = 0;
if (step==9) for(i=0; i<(sizeof(Message1)-1); i++) USIC0_CH1->IN[0] = Message1;
// if (step==19) for(i=0; i<(sizeof(Message2)-1); i++) USIC0_CH1->IN[0] = Message2;
}
void initUART(void)
{
//Kernel State Configuration Register - Module Enable + Bit Protection for MODEN
USIC0_CH1->KSCFG |= (1 << USIC_CH_KSCFG_MODEN_Pos) | (1 << USIC_CH_KSCFG_BPMODEN_Pos);
//Fractional divider mode selected
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_DM_Msk, USIC_CH_FDR_DM_Pos, 2);
//Step value
WR_REG(USIC0_CH1->FDR, USIC_CH_FDR_STEP_Msk, USIC_CH_FDR_STEP_Pos, FDR_STEP);
//PreDivider for CTQ, PCTQ = 0, Denominator for CTQ, DCTQ = 16
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PCTQ_Msk, USIC_CH_BRG_PCTQ_Pos, BRG_PCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_DCTQ_Msk, USIC_CH_BRG_DCTQ_Pos, BRG_DCTQ);
WR_REG(USIC0_CH1->BRG, USIC_CH_BRG_PDIV_Msk, USIC_CH_BRG_PDIV_Pos, BRG_PDIV);
//Configuration of USIC Shift Control
//Transmit/Receive LSB first is selected, Transmission Mode (TRM) = 1, Passive Data Level (PDL) = 1
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_PDL_Msk, USIC_CH_SCTR_PDL_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_TRM_Msk, USIC_CH_SCTR_TRM_Pos, 1);
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_SDIR_Msk, USIC_CH_SCTR_SDIR_Pos, 0); //自己加上的
//Set Word Length (WLE) & Frame Length (FLE)
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 7);
// WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, 10); //自己加,经验证不可行
WR_REG(USIC0_CH1->SCTR, USIC_CH_SCTR_WLE_Msk, USIC_CH_SCTR_WLE_Pos, 7);
//Configuration of USIC Transmit Control/Status Register
//TBUF Data Enable (TDEN) = 1, TBUF Data Single Shot Mode (TDSSM) = 1
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDEN_Msk, USIC_CH_TCSR_TDEN_Pos, 1);
WR_REG(USIC0_CH1->TCSR, USIC_CH_TCSR_TDSSM_Msk, USIC_CH_TCSR_TDSSM_Pos, 1);
//Configuration of Protocol Control Register
//Sample Mode (SMD) = 1, 1 Stop bit is selected, Sample Point (SP) = 2, Pulse Length (PL) = 0
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SMD_Msk, USIC_CH_PCR_ASCMode_SMD_Pos, 1);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_STPB_Msk, USIC_CH_PCR_ASCMode_STPB_Pos, 0);
WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 9);
// WR_REG(USIC0_CH1->PCR_ASCMode, USIC_CH_PCR_ASCMode_SP_Msk, USIC_CH_PCR_ASCMode_SP_Pos, 3); //自己加上的
//TBIF is set to simplify polling
WR_REG(USIC0_CH1->PSR_ASCMode, USIC_CH_PSR_TBIF_Msk, USIC_CH_PSR_TBIF_Pos, 1);
//Configuration of Transmitter Buffer Control Register
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_LIMIT_Msk, USIC_CH_TBCTR_LIMIT_Pos, 0);
//Configuration of Channel Control Register
//parity generation is disabled
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 2);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_PM_Msk, USIC_CH_CCR_PM_Pos, 0);
//Data Pointer & Buffer Size for Transmitter Buffer Control - DPTR = 64, SIZE = 6
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos, 0x06000040);
}
//----PIN-SETUP-------------------------------------------------------------------------------------
P0_0_set_mode(OUTPUT_PP_GP);
P1_2_set_mode(OUTPUT_PP_AF7);
P1_3_set_mode(INPUT);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
above are the related codes,the visual COM on computer displays "UUUUU_UUU_UUUUUUUU_UUUhUUU__",I select U because its ASCII is 01010101b whose 0 and 1 distribute evenly.The displayed codes on computer would be all wrong if I didn't select U as the member of array message1.It seems that the displayed codes on computer is the result of right shift one bit of one's complement of the members from array message1.
I don't know why and hope for some help.
- Tags:
- IFX
- xmc1300_uart
4 Replies
Not applicable
Sep 10, 2014
03:27 AM
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Sep 10, 2014
03:27 AM
Hi Shaojun,
Why don't try UART001_Example3_XMC13 using Apps?
BR,
Zain
Why don't try UART001_Example3_XMC13 using Apps?
BR,
Zain
Not applicable
Oct 02, 2014
05:01 AM
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Oct 02, 2014
05:01 AM
I had the same experience. Data from the Uart is shifted one bit and complemented.
I did try UART001_Example3_XMC13 as suggested. Data out the uart is also not as expected.
Anybody have a Uart example for the XMC13 that works?
I did try UART001_Example3_XMC13 as suggested. Data out the uart is also not as expected.
Anybody have a Uart example for the XMC13 that works?
Not applicable
Oct 02, 2014
11:08 AM
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Oct 02, 2014
11:08 AM
OK, I was able to fix this by setting DOCFG (Data Output Configuration) to 0x03. This is in the Shift Control Register SCTR.
According to the reference manual this will invert the shifted data value. Not sure why I need to invert the bits before sending out the port, but it works now.
According to the reference manual this will invert the shifted data value. Not sure why I need to invert the bits before sending out the port, but it works now.
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Not applicable
Oct 06, 2014
10:25 PM
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Oct 06, 2014
10:25 PM