What is the compare in Lockstep from AURIX.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Not applicable
Hello.
This is ChaeHong Yi.

I'm testing the TC275 board.

Following the tc27xb datasheet, the LCL (Lockstep Comparator Logic) can be enabled or disabled by LCLCON0 and LCLCON1 registers.
I know that when Lockstep is enabled, after executing the same commands, the results of two cores will be compared together.
If those results are different then alarm flags in SMU module will be set.
Is Lockstep replication to core0 from core1?
Or we have to coding each other core?

It compares each other. when consist of other code about core0 and core1(other functions, variables)??
otherwise, logic of core0 has to replicate the core1. it means ignoring current hand coding about core1??

In addition :
If we have three cores 0, 1, 2, where core 0 is a functional core (master), core 1 and core 2 are checker cores. When we enable Lockstep in core 1 and disable lockstep in core 2 we will have a pair of functional and checker cores 0 and 1.
To check lockstep comparator, we just need to write a program in single core style on master core (core 0), compile and execute it on core 0. We dont need to copy source code of that program to core 1. Every jobs related to checking outputs is done automatically by checker core 1. Is my thinking correct?

Thank you very much for you guys help.

Best regards,
ChaeHong Yi.
0 Likes
3 Replies
µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received
Gary Yi wrote:
Is Lockstep replication to core0 from core1?
Or we have to coding each other core?

It compares each other. when consist of other code about core0 and core1(other functions, variables)??
otherwise, logic of core0 has to replicate the core1. it means ignoring current hand coding about core1??

If we have three cores 0, 1, 2, where core 0 is a functional core (master), core 1 and core 2 are checker cores. When we enable Lockstep in core 1 and disable lockstep in core 2 we will have a pair of functional and checker cores 0 and 1.
To check lockstep comparator, we just need to write a program in single core style on master core (core 0), compile and execute it on core 0. We dont need to copy source code of that program to core 1. Every jobs related to checking outputs is done automatically by checker core 1. Is my thinking correct?

Your thinking is basically correct. Each checker cores is tied to its master core - you cannot program the checker cores independently. A TC27x has a CPU0 with lockstep, a CPU1 with lockstep, and a CPU2 without.

As the User Manual states:
Each core capable of lockstep also has a continuously running background self test of the lockstep comparator.

You can test the lockstep comparator with the LCLTEST.LCLT0/LCLT1 bits (or the LockStepTst_LockStepTst function in Infineon's SafeTlib software library).
0 Likes
Not applicable
Could anyone please explain the basic working of Lockstep at Hardware level? Whether a lock step capable core(e.g. Core0 in TC275) has additional sub-core (or CPU) apart from the main core to execute the instructions simultaneously? If it is so, how these cores share the resources like registers, stack etc within the same core?
0 Likes
lock attach
Attachments are accessible only for community members.
Not applicable
Please find attached a basic overview of the lockstep architecture. BR Martin
0 Likes