Apr 29, 2014
04:45 AM
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Apr 29, 2014
04:45 AM
3 Replies
May 01, 2014
10:34 PM
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May 01, 2014
10:34 PM
Ing99 wrote:
Hi Infineon,
at SCU PLL DAVE doesn't calculate optimal values. External clock of 40MHz should result in:
P=4
N=48
K2=4.
Instead DAVE sets:
P=3
N=36
K2=4.
DAVE doesn't use the recommended even value for P to minimize jitter.
Best regards,
Wolfgang
Yes, I found this statement in the XMC4500 reference manual. Pls let me check with the module owner.
It is strongly recommended to apply even value of P and USB Clock Divider (referred to
as USBDIV divider) parameters in order to minimize PLL output clock jitter effect. Please
find PLLUSB configuration examples values in Table 11-6.
Not applicable
Jun 13, 2014
02:10 AM
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Jun 13, 2014
02:10 AM
Hello,
I am also interested on this issue. Are there any news?
Sincerely yours,
MeB
I am also interested on this issue. Are there any news?
Sincerely yours,
MeB
Jun 16, 2014
11:03 PM
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Jun 16, 2014
11:03 PM
Hi MeB,
I had feedback to them on this issue and the DAVE3 team should be working on this.
Best Regards
Travis
I had feedback to them on this issue and the DAVE3 team should be working on this.
Best Regards
Travis