RX FIFO of a USIC with PEC interrupt?

[#1]

Hello everyone:

I am using a serial communication, ASC at 1Mbps. For transmitting I am using a PEC mechanism that works pretty fine. I have tried to use this method for the reception but it doesn’t work, so I have implemented the reading of the RX-FIFO data byte per byte. But I have the problem that the transmission is faster as the reception and when the software is still reading a received data packet ( a FIFO block), arrived the next block and then sometimes the RX interrupt is lost. Someone knows how can I do the RX-FIFO reading faster? Or have an idea?
The system should be very fast so a delay in the transmission is not an option

Thanks

[#2]

Hi Jeimy,

When you said the PEC is not working for receiving, may I know what you are facing?
I think the PEC should be fastest way to get your data from the receive buffer to the location you need.

[#3]

Hi Jackson,

when the PEC transfers finish, it does not active the RX interrupt. Debugging the software I can see the first data block in the destination register which its configured in the PEC destination pointer.
The FIFO interrupt is configured with the GLVL = 0; ILVL = 0xD; GPX = 0; and the IE enabled
The PECC register is 0x5310 and it is the PEC 4.
The interrupt is active with the second FIFO block, that means when the RX FIFO has reached its level, and not when the PEC transfers has finished.
I don't know what I am doing wrong 😞 and I would appreciate any help or idea.
Thanks a lot

[#4]

Hi Jeimy,

Did you configure using DAVE code generator?
You can enable End of PEC (EOP) interrupt from the PEC channel configuration.
Then, go to the Interrupt bubble to configure the EOP interrupt.
Now you can have an interrupt after the PEC operation.
I hope this is what you want. 🙂

[#5]

Hello Jackson,
Thank you for your help. I have already tried with the EOP and changed the Uart CCR register to interrupt with a reception and not with the RX-FIFO level. I did not have so, and therefore the interrupt was lost. Now the PEC interrupts, but when the serial message is bigger as one RX-FIFO size, the second interrupt is lost. :rolleyes:

On the other hand, as the project I am developing requires that the communication has not errors like data lost, and the PEC does not use the FIFO (or at least I think so), there is the risk to lose the data if the interrupt is attended too late. For that reason, it was decided to do not use the PEC mechanism for the reception. 😞

Anyway thanks a lot for your posts:)