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Jan 28, 2014
04:28 AM
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Jan 28, 2014
04:28 AM
I am using 4 synchronously sampled VADC channels @ 1.25 Msps transferred to 4 circular buffers using GPDMA0.
In the DMA interrupt (block transfer complete = inner loop) the GPDMA0_CHx->DAR is pointed to the next buffer window, GPDMA0->MASKBLOCK, GPDMA0->CHENREG and GPDMA0->CLEARBLOCK are set to enable the next transfer.
In an outer loop I check for new windows and do an evaluation of the buffer content. If the window content has a given frequency content the channel should be suspended. What is the correct procedure using the DMA003/NVIC_DMA001 apps or direct register control? When all channels are suspended, the inner loop shold stop (DMA IRQ). Should I reset GPDMA0->DMACFGREG.DMA_EN, or is there another way?.
At a later time (after some more data processing etc.) I wish to restart the DMA, enable all channels and restart transfer. Correct procedure at this point?
I have tried a lot of different stuff so far, but even if I am able to stop the individual channels (by not setting the corresponding CHENREG and MASKBLOCK bits), I later have problems when trying to restart them.
Thanks,
/Åse Maj
In the DMA interrupt (block transfer complete = inner loop) the GPDMA0_CHx->DAR is pointed to the next buffer window, GPDMA0->MASKBLOCK, GPDMA0->CHENREG and GPDMA0->CLEARBLOCK are set to enable the next transfer.
In an outer loop I check for new windows and do an evaluation of the buffer content. If the window content has a given frequency content the channel should be suspended. What is the correct procedure using the DMA003/NVIC_DMA001 apps or direct register control? When all channels are suspended, the inner loop shold stop (DMA IRQ). Should I reset GPDMA0->DMACFGREG.DMA_EN, or is there another way?.
At a later time (after some more data processing etc.) I wish to restart the DMA, enable all channels and restart transfer. Correct procedure at this point?
I have tried a lot of different stuff so far, but even if I am able to stop the individual channels (by not setting the corresponding CHENREG and MASKBLOCK bits), I later have problems when trying to restart them.
Thanks,
/Åse Maj
2 Replies
Feb 03, 2014
01:12 PM
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Feb 03, 2014
01:12 PM
Hi,
Setting bit GPDMAx_CHy_CFGL.CH_SUSP will halt all transfers from the source peripheral.
To remove the channel from the suspension state write a 0 to the GPDMAx_CHy_CFGL..CH_SUSP register. The DMA transfer completes in the normal manner.
I hope this helps.
Please do not hesitate to contact again in case of further questions arise.
Best regards,
Jesus
Setting bit GPDMAx_CHy_CFGL.CH_SUSP will halt all transfers from the source peripheral.
To remove the channel from the suspension state write a 0 to the GPDMAx_CHy_CFGL..CH_SUSP register. The DMA transfer completes in the normal manner.
I hope this helps.
Please do not hesitate to contact again in case of further questions arise.
Best regards,
Jesus
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Feb 17, 2014
07:20 AM
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Feb 17, 2014
07:20 AM
Hello Jesus,
Well, yes. CH_SUSP does suspend a DMA channel. And, I finally found a way to solve this which involves suspending each channel until none are running, then disable the DMA IRQ (otherwise the interrupt is immediately active as there are no data to transfer, causing no other code to be reached). To be able to restart the whole thing I also need to disable the DMA channels (CHENREG), set the DAR, reset CH_SUSP, reenable DMA channels (CHENREG, MASKBLOCK, CLEARBLOCK), clear pending DMA IRQs and reenable DMA IRQ. In addition, support has suggested stopping and restarting the VADC groups as part of this procedure. Phew!
Thanks, anyway. 😮
/Åse Maj
Well, yes. CH_SUSP does suspend a DMA channel. And, I finally found a way to solve this which involves suspending each channel until none are running, then disable the DMA IRQ (otherwise the interrupt is immediately active as there are no data to transfer, causing no other code to be reached). To be able to restart the whole thing I also need to disable the DMA channels (CHENREG), set the DAR, reset CH_SUSP, reenable DMA channels (CHENREG, MASKBLOCK, CLEARBLOCK), clear pending DMA IRQs and reenable DMA IRQ. In addition, support has suggested stopping and restarting the VADC groups as part of this procedure. Phew!
Thanks, anyway. 😮
/Åse Maj