ESD sensitivity of semiconductor devices is increased in general by every step forward in miniaturization.
On the other hand miniaturization is very important to bring production cost down and functionality / signal speed up.
In case of an ESD strike a certain maximum voltage must not exceed at the IC I/O s. Otherwise an ESD damage is encountered.
Moving forward in miniaturization internal isolation structures are reduced (e.g. the gate oxide thickness of a MOS-FET) and size if internal ESD protection structures is shrinked as well.
This has an impact to the maximum possible voltage at the IC I/O s in the case of an ESD strike. This value is continuously going down by every step forward in technology nodes.
Reasonable ESD protection (according System Level, IEC61000-4-2) of the IC in the application has to be provided by dedicated TVS diodes on the PCB, collaborating in a tailored way with the internal IC ESD protection.
