+ Reply to Thread
Page 1 of 2 1 2 LastLast
Results 1 to 10 of 12

Thread: XMC4700 UART problem

  1. #1
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375

    XMC4700 UART problem

    I'm seeing a problem with the UART FIFOs on a XMC4700.
    Perhaps there is an errata?

    The "A" in UART stands for Asynchronous.
    I'm trying to send 8 bytes , but I'm also receiving data at the same time. Most of the time, the transfers are all good.
    But, occasionally, the transmit data is not what I expect. The transmit data appears to part of the data just received.

    Initialization code:
    Code:
       // Setup interrupts
        // Remote , BBB
        XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 1U);
    
        // Set service request for tx FIFO transmit interrupt
        XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 1);
     
        // Set priority and enable NVIC node for transmit interrupt SB USIC0_CH0 base = 84 + 1 (Nodepointer above)=85
        NVIC_SetPriority((IRQn_Type)85, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
        NVIC_EnableIRQ((IRQn_Type)85);
    
        // Turn off source of interrupts. They're turn on when FIFO is full
        UART_SB.channel->TBCTR  = UART_SB.channel->TBCTR & ~USIC_CH_TBCTR_STBIEN_Msk;
    
        // RX Interrupts
        // smallest frame is 6 bytes
        // Protocol is poor, the 2nd byte "length" is not accurate if any data is escaped
        // assume worst, go with 1 (0).
        // Can't switch trigger limits on the fly, need to go with 1
    
        XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 0U);
     
        // Set service request for Rx FIFO transmit interrupt
        XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 0);
        XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE, 0);
     
        // Set priority and enable NVIC node for receive interrupt SB USIC0_CH0 base = 84 + 0 (Nodepointer above)=85
        NVIC_SetPriority((IRQn_Type)84, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
        NVIC_EnableIRQ((IRQn_Type)84);
    I've attached a scope capture of the problem.
    The XMC4700 receives a CAN message (CAN 2F0 1 2E) on left. It converts this to a UART stream, should be "31 08 53 02 F0 2E xx 32". But as can be seen on "RS-232(RX) ... "31 08 53 00 00 00 70 32". The 4700 is transmitting this.
    Just above is "RS232(Tx) ... 31 0A 53 03 81 00 00 00 70 32". The "70 32" is cut off a bit, but its there.
    It appears that the transmit is read from the RX FIFO!
    Is there some kind of race condition in the hardware?
    And more important, is there a work around?
    ?????? ?????? tek00008.png‎  

  2. #2
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    Update:
    I added another UART and sent the same data to it. Original on Uart 0 Ch0, the new one on Uart 0 Ch 1.
    When it fails, the new UART has the correct data.
    So, pointing at a UART problem or perhaps I have a configuration issue.

  3. #3
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    There is still a UART problem.

    I've managed to circumvent it by using another UART.
    I do have a working system again, but I luckily only needed to add one jumper wire.

  4. #4
    Intermediate Intermediate amanning will become famous soon enough
    Join Date
    Oct 2015
    Posts
    132
    Points
    288.486328125
    In your initialization code I cannot see where you set the size and starting position of the FIFOs. As the FIFO RAM is shared by 2 channels, it is very important to set the starting position of each FIFO correctly. I usually use 4 FIFOs each of 16 Bytes, starting at 0, 16, 32, and 48.

  5. #5
    Intermediate Intermediate Aashita_Raj is on a distinguished road Aashita_Raj's Avatar
    Join Date
    May 2021
    Posts
    11
    Points
    260
    Hi @TimFlynn,

    Can you please attach your entire project here, so that we can check at our end?

    Best Regards,
    Aashita

  6. #6
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    Project attached.
    Using Dave Apps.
    This is the working version. UARTs configured as; UART_SB_RX, Direct, Receive FIFO enable & = 32. Tx FIFO disabled. USIC/0/ch/0
    UART_SB_TX, Direct, Tx FIFO enable & = 32. Rx Fifo disabled. Usic/1/ch/0

    This version works as required, but I had to modify boards for this configuration.
    Prior version, that didn't work, had RX & TX on same USIC & channel with fifos = 16 for each Rx & Tx.
    This prior version mostly worked, except when an Rx was occurring about the same time as a Tx.
    ?????

  7. #7
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    Setup is in the Dave app. I also typically use 16 bytes per.

  8. #8
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    Any update?

  9. #9
    Beginner Beginner TimFlynn is on a distinguished road
    Join Date
    Jun 2016
    Posts
    83
    Points
    470.68359375
    Anyone? please

  10. #10
    Intermediate Intermediate ErnieT is on a distinguished road
    Join Date
    Feb 2018
    Location
    Germany
    Posts
    47
    Points
    367.5
    Hello Tim,

    can you change the project to send manually (no FIFO)?

    Also, are the FIFOs for different purposes correctly placed, so they don't overlap? Because of this:
    This prior version mostly worked, except when an Rx was occurring about the same time as a Tx.
    You need to set TBCTR.DPTR. If both RX and TX FIFOs start at position 0, they will overlap and you'll see strange behaviour.

    Best regards,
    ErnieT
    Last edited by ErnieT; Jul 31st, 2021 at 02:49 AM.

+ Reply to Thread
Disclaimer

All content and materials on this site are provided “as is“. Infineon makes no warranties or representations with regard to this content and these materials of any kind, whether express or implied, including without limitation, warranties or representations of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, whether express or implied, is granted by Infineon. Use of the information on this site may require a license from a third party, or a license from Infineon.


Infineon accepts no liability for the content and materials on this site being accurate, complete or up- to-date or for the contents of external links. Infineon distances itself expressly from the contents of the linked pages, over the structure of which Infineon has no control.


Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Usage Terms of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Usage Terms of this site. Infineon reserves the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.