XMC4300/4800: SPI master with FIFO and automatic chip select

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User14604
Level 4
Level 4
First solution authored
Hello!

I'm implementing a SPI master to interface a A/D converter chip. XMC is communication master.
The ADC receives 16 bit per transfer. The transfer starts with a chip select and ends with chip deselect.

I'd like to use a FIFO buffer to asynchronously send to and receive from the ADC. The FIFO buffer must contain 2 transfers (total of 16 bits). Something like this.
chip select 1 --> data in 1 --> chip deselect 1 --> programmable wait time -> chip deselect 2 ---> data in 2 ---> chip deselect 2

I assume the frame length (SCTR register) needs to be set to 16.
I also assume that the programmable wait time between transfers needs to be set in BRG register with USIC_CH_BRG_DCTQ_Pos.

1. Is automatic chip selection possible with using a FIFO? If so, are there any examples or hints on how to implement this
2. Are my assumptions above correct?

Thank you for reading,
Ernie T.
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Vasanth
Moderator
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250 sign-ins 500 solutions authored First question asked
Hi Ernie,

Could you please let us know why do you have multiple chip selects? Additionally could you let us know the external ADC you are using?

Please find the application note for USIC for reference.

Best Regards,
Vasanth

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Vasanth
Moderator
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Moderator
250 sign-ins 500 solutions authored First question asked
Hi Ernie,

Could you please let us know why do you have multiple chip selects? Additionally could you let us know the external ADC you are using?

Please find the application note for USIC for reference.

Best Regards,
Vasanth
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User14604
Level 4
Level 4
First solution authored
Hello Vasanth,

thanks for the help and link.

I'm using the Analog Devices AD7386, a 4-channel 16-bit with two parallel converters (datasheet -> https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386.pdf).

The SPI is serving only this device, so there's only a single chip select line. In my example, "chip select 1" and "chip select 2" refer to the same chip select line, but different transfers. Each transfer starts with a chip select assertion and stops with a chip select de-assertion.
Each transfer writes 32 bits and reads back 32 bits. Those 32 bits contain 2 out of 4 ADC channels, therefore 2 transfers are required to read full 4 channels.

Best regards,
Ernie
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