Apr 02, 2021
03:21 AM
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Apr 02, 2021
03:21 AM
Hi guys,
I am using TC397 step B for my Ethernet project with Eth driver provided by Infineon.
After the Eth driver is initialized, the bit SWR of DMA_MODE is set to 1 and never returns to 0.
as I read from datasheet, the SWR is software reset bit, it is normally set by software.
I do not know why the bit is set just after initialization. I think this is not the correct behavior.
Do you know how to fix it? Any causes can lead to this behaviors?
Thank you,
Dang Ho
I am using TC397 step B for my Ethernet project with Eth driver provided by Infineon.
After the Eth driver is initialized, the bit SWR of DMA_MODE is set to 1 and never returns to 0.
as I read from datasheet, the SWR is software reset bit, it is normally set by software.
I do not know why the bit is set just after initialization. I think this is not the correct behavior.
Do you know how to fix it? Any causes can lead to this behaviors?
Thank you,
Dang Ho
7 Replies
Apr 02, 2021
10:06 AM
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Apr 02, 2021
10:06 AM
Hi DangHo,
maybe there are some synchronization issues. Please look at GETH_AI.H001 for MII and RMII and GETH_AI.H002 for RGMII from the Errata sheet (Rel. 1.4, 2020-10-23).
Regards,
Jens
maybe there are some synchronization issues. Please look at GETH_AI.H001 for MII and RMII and GETH_AI.H002 for RGMII from the Errata sheet (Rel. 1.4, 2020-10-23).
Regards,
Jens
Apr 02, 2021
10:25 AM
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Apr 02, 2021
10:25 AM
Hi DangHo,
try the GETH_TC.002 for RGMII and GETH_AI.H001 for MII and RMII from TC39x BD-Step Errata sheet.
The Errata sheet from the Post above is for TC36x AA Step.
Regards,
Jens
try the GETH_TC.002 for RGMII and GETH_AI.H001 for MII and RMII from TC39x BD-Step Errata sheet.
The Errata sheet from the Post above is for TC36x AA Step.
Regards,
Jens
Apr 06, 2021
02:11 AM
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Apr 06, 2021
02:11 AM
Please see description of the SWR bit:
This bit is automatically cleared after the reset operation is complete...
Setting 1 sets. Self-cleared. Setting 0 has no effect.
This bit is automatically cleared after the reset operation is complete...
Setting 1 sets. Self-cleared. Setting 0 has no effect.
Apr 06, 2021
11:37 PM
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Apr 06, 2021
11:37 PM
Hi Jen,
Thank for your response. I just realized that my MCU is not provided with GREFCLK.
Is there any option that allow RGMII mode work without GREFCLK?
Thank you,
Dang
Thank for your response. I just realized that my MCU is not provided with GREFCLK.
Is there any option that allow RGMII mode work without GREFCLK?
Thank you,
Dang
Apr 07, 2021
12:26 AM
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Apr 07, 2021
12:26 AM
No, there is no option which allow RGMII mode without clock. Please see from description of SWR bit:
Note: The reset operation is complete only when all resets in all active clock domains are de-asserted.
Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion.
The time to complete the software reset operation depends on the frequency of the slowest active clock.
Note: The reset operation is complete only when all resets in all active clock domains are de-asserted.
Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion.
The time to complete the software reset operation depends on the frequency of the slowest active clock.
Apr 07, 2021
06:34 AM
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Apr 07, 2021
06:34 AM
Hi DangHo,
please have a look at P11.5. There you have the GETH_GREFCLK (Gigabit Reference Clock input for RGMII (125 MHz high precission)).
Regards,
Jens
please have a look at P11.5. There you have the GETH_GREFCLK (Gigabit Reference Clock input for RGMII (125 MHz high precission)).
Regards,
Jens
May 05, 2021
12:49 AM
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May 05, 2021
12:49 AM
JensM wrote:
Hi DangHo,
please have a look at P11.5. There you have the GETH_GREFCLK (Gigabit Reference Clock input for RGMII (125 MHz high precission)).
Regards,
Jens
Hi Jens,
After adding the clock on P11.5, my issue can be solved now. Thanks for your support.
I close this topic here..
Thanks all for your support,
Dang Ho