Aurix tc1.6.2p dcache

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
User21527
Level 1
Level 1
Hi there,

i am currently working with the TC38x with the TC1.6.2P. I am wondering if the DCACHE invalidates the data saved by itself. Assume a data is already cached in the DCache, but it is changed in the originall destination. Does the DCache detect that change or do i have to refresh it?
I can not find anything regarding that topic in the datasheet. For the Program Cache it is described, but not for the Data Cache.

Thank you for your help.

Best regards
Sven
0 Likes
2 Replies
TBencher
Level 6
Level 6
25 solutions authored 25 likes received 5 questions asked
Hi Sven96,

I found maybe something useful in the TriCoreTM TC1.6.2 core architecture manual - Instruction set 32-bit Unified Processor Core.
There are instructions to do a manually invalidation, like

CACHEA.I, CACHEA.W, CACHEA.WI, CACHEI.I, CACHEI.W, CACHEA.W, CACHEI.WI, CACHEA.WI

But, you can also do a complete invalidation via the Overlay Control Register OVCCON.

I found also this:

Data accesses to the memory will be cached by the CPU if a data cache is present and enabled.The CPU is permitted to perform speculative data fetches to the memory.

I think if you use cashed memory -data cache present and enabled assumed-, the data cache (line) will be invalidated in the moment you write to it.


Regards,

Jens
0 Likes
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
There is no automatic cache coherency on the AURIX.

If you need to force CPU writes to occur, use the cache W instructions to force a writeback.

If you need to force the CPU to re-fetch remote data, use the cache I instructions to invalidate a cache line, discarding the contents.

OVCCON invalidates the entire data cache and takes several cycles to complete.

You can also consider using cached LMU addresses (segment 9) and uncached LMU addresses (segment B).
0 Likes