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Thread: Parasitic turn on in IPT015N10?

  1. #1
    Beginner Beginner david.molony is on a distinguished road
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    Parasitic turn on in IPT015N10?

    So as per the below image, I am seeing some considerable gate bounce as the MOSFETs transition from low to high switch. This is a half bridge (part of a 3 phase bridge) with IPT015N10 MOSFETs and 2EDL23N gate drivers, with 2.2R resistors on the gate.

    I am running ~600ns dead time, and have verified (actually on another thread on the gate driver forum, that there is a peak of about 1A into the FETs gates. The switching looks really nice. I started investigating this only because it turns out my dead time was too short (accidentally set the dead time at 178ns owing to programming whoopsie)

    When designing this, I followed the appnote "Parasitic Turn-on of Power MOSFET – How to avoid it?":
    https://www.infineon.com/dgdl/Parasi...1eee756cee5475

    From this, I ascertained that the parasitic gate bounce witha 75V DC bus would be given roughly by:
    75V*Crss/(Ciss-Crss)=75*80pF/(12000pF-80pF) = 0.5V

    The ratio CGS/CGD is 150, which for a 75V rail, and by analogy to the appnote statement " is completely
    safe against parasitic turn-on"

    The problem is as in the pics below:
    Ringing on the gate trace
    Click image for larger version

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    This is how I am probing the gate - can't really think how to get a better measurement than this...
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    This clearly shows that the gate bounce at the switching event is much higher than the calculation from the appnote shows. There is no current flowing (nothing attached to the switch node) so this isn't intuitively inductive coupling, and probing the gate driver side of the gate resistor shows a lower amount of bounce, by approximately 1/3 - the ratio I would expect given the 2.2R resistor and the ~5ohm driver pull down impedance.

    The gate driver has a very solid ground path between the PGnd and the FET source, a plane with the gate trace routed through it There is a ground plane directly below it. This is taken on the low side FET.

    So the question is: Why am I getting this amount of bounce? Pretty much 10x as much as the appnote calculates I should get. Is it real, or is there some other explanation I am missing?
    Further question: Is this a problem? It's only a 25ns wide blip, maybe that is so short that the effect is negligible?
    Further question: If it is a problem, what should I do about it? I chose these FETs because they looked completely safe against parasitic turn on, I don't really want to go down the route of generating negative gate drive voltages etc, since this would eliminate my use of the 2EDL's over current protection and generally involve a lot more board space.

  2. #2
    Beginner Beginner david.molony is on a distinguished road
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    Incidentally, I have another board with these FETs, with a technically slightly inferior layout and NCV5183 gate drivers (similar to the higher drive capacity but no seperate power ground) and I observe exactly the same behaviour.

    I have another board, with the NCV5183 drivers and some TI CSD19536 FETs (TO-263) and an even worse layout, and the problem is much worse. However, I have been pushing 40A continuous through this, 100A short term with 55V bus and have not had issues so... maybe this is just an irrelevant artifact?

  3. #3
    Beginner Beginner david.molony is on a distinguished road
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    Jut an update with an image at 10x probe input, which seems to show there is some ringing on the scope cable that the extra probe resistance damps.

    Click image for larger version

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    And there it is in relation to the switch node switching time.
    Click image for larger version

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    Last edited by david.molony; Feb 21st, 2021 at 09:26 AM.

  4. #4
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    Abhilash P is on a distinguished road
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    Hi,

    From the data you have provided we tried analyzing the possible cause for the surge. Can you please provide the answers for the following questions so that it would be more helpful for us to debug and find the exact cause for this issue.
    1) If the efficiency is concerned for this application ( so that we can work on modifying gate resistance )
    2) Oscilloscope shot of Vgs & Vds and Vgs & Vdg during the gate surge instance
    3) Maximum value of gate resistance that can be added.
    4) Please verify if the components are placed accurately on the PCB and there is no noise interference
    5) Please verify the Trr of the diode

    Regards,
    Abhilash P
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  5. #5
    Beginner Beginner david.molony is on a distinguished road
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    ^^ You seem to have a spam account here that needs disabling...

    Thanks for the reply!

    To your questions:
    1) Efficiency is of utmost importance, mainly from the perspective of keeping the system small, high power density - inefficiency cause heat that will need removing with a bigger heatsink.
    2) I don't understand... Isn't that exactly what I provided in my first post?
    3) Max value of gate resistance... There is no max value. If it works, allows ~30kHz switching and does not cause great inefficiency, I would happily put 1Mohm. Do you mean can I try swapping out for various other resistors? This is feasible. What values would you recommend?
    4) Components are placed accurately. The PCB otherwise works exactly as expected. It is a 4 layer board with continuous ground plane on the top-inner layer assembled by machine.
    5) How do I do this? Infineon's datasheet says 103ns.
    https://www.infineon.com/dgdl/Infine...4ac94680661aff

    I still have no explanation for this, it is still present, I am still concerned but the boards still work absolutely fine.

  6. #6
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    Abhilash P is on a distinguished road
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    Hi,

    Can you please share the circuit that you have rigged up. It helps us in analyzing to what extent we can increase the gate resistance.

    Regards,
    Abhilash P
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  7. #7
    Beginner Beginner david.molony is on a distinguished road
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    Below, excerpts from the schematic and layout of 1/3 phases. I am afraid I cannot post the full thing online. I have circled the 2.2R gate resistors in blue.
    You can see there is a solid net returning the PGnd to the 2EDL, and the gate drive signal runs through the middle of it.There is a ground plane running directly below it. (yellow is a continuous plane on the top inner board layer).

    I'll add that I have verified the pulses with two other much more expensive, higher end scopes with ground springs and 100MHz+ bandwidth, I'd post the results but it's pointless, they are identical... I didn't bother to save them.

    I am interested in knowing the route cause of this spike, not merely slowing the circuit down to eliminate it (specifically I want to know why it looks exactly like a Miller bounce that the Infineon appnote says it should be completely immune to).

    I am wondering:
    Is the Infineon appnote wrong?
    Are the FETs counterfeit (they seem to perform adequately otherwise, but the board was assembled by a low cost Chinese SMT outfit so it is a possibility)?
    Is there another effect (source inductance for example, though at zero current I struggle to see why this would be the cause... parasitic output capacitance perhaps?


    Click image for larger version

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    Last edited by david.molony; Mar 28th, 2021 at 03:35 AM. Reason: Add note about scope accuracy

  8. #8
    Beginner Beginner david.molony is on a distinguished road
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    I think I have cleared this up:

    I artificaially induced a step change on the MOSFET Vds, and scoped the Vgs. Can clearly see the miller step change and the inductive transition artifact.
    Click image for larger version

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    To do this, I removed the gate driver resistor. I did this on another board, with the NCV5183 gate driver, since that one is more... disposable. Same IPT015N10 FET.
    Click image for larger version

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    I did this for a number of Vds steps, and got the following result:
    Click image for larger version

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    Looks like my previous observation is a superposition of a miller effect that will always remain below the gate threshold and an inductive artifact. Also apparent that the Crss being quite high at lower Vds is a bit misleading; citing Crss at 50V as the derivative of the charge, not the cumulative effect of the charge is... maybe technically correct but a bit misleading and not helpful in the context of the appnote.

    So all is probably fine, no need to fiddle with slowing things down, bigger better gate drivers/whatever.

    But Infineon, that appnote needs revising. It is NOT correct given the way you cite your Crss values. In my case it will be fine regardless, but in many other cases it may result in design failures.

  9. #9
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    Hi David,

    Thank you for letting us know about the issue in the app note. We are working internally on the revision.

    Regards,
    Abhilash P
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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