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Thread: Clock Control Unit – TC3777

  1. #1
    Intermediate Intermediate nadeem_syed is on a distinguished road
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    Clock Control Unit – TC3777

    Can you please clarify below questions based on the figure 87 in section 10.5.1 of AURIX™ TC3xx User manual V 1.3.0.

    1. Can the MUX selection of fsource0, fsource1 and fsource2 be configured separately. For example can I configure fsource0 = fPLL0 fsource1 = fBack and fsource2 = fBack ?
    2. Which register has the MUX selection configuration for fsource0 ?
    3. Which register has the MUX selection configuration for fsource1 ?
    4. Which register has the MUX selection configuration for fsource2 ?
    5. For fsource1 DIV2 can be selected and register is specified as CCUCON1.PLL1DIVDIS. I don’t see this register at all in section 10.5.1.3, is this a typo and the register is PERPLLCON0. DIVBY ?
    ?????? ?????? CCU_Snapshot.jpg‎  

  2. #2
    Intermediate Intermediate nadeem_syed is on a distinguished road
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    Dear Community Members,

    Any thoughts on this questions ?

  3. #3
    Intermediate Intermediate cwunder will become famous soon enough
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    This is my understanding:

    Click image for larger version

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    CCUCON1.PLL1DIVDIS is bit 7 of the CCUCON1 register...

    The user's manual I am referring to is AURIXTC3XX_UM_part1_v1.6.pdf
    Last edited by cwunder; Jan 19th, 2021 at 08:51 AM.

  4. #4
    Intermediate Intermediate nadeem_syed is on a distinguished road
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    Thank you so much !!! This makes sense. I have clear understanding now and its matches with MCAL settings what I am trying to configure.

    I will get the new version of the User manual, my version looks like does not have this information

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