Linker Error - TC277 Tasking

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DSRnathan
Level 3
Level 3
50 sign-ins 25 replies posted 25 sign-ins
i was trying to locate the trap table just before the Interrupt table and implement as shown below,
#define TRAPTAB (INTTAB - 0x100) // aligned to 256 bytes. But i ended up getting a error as shown below.

"C:\\Program Files\\TASKING\\TriCore v6.3r1\\ctc\\bin\\amk" -j8 all
Linking to RTOS_BSW.elf
ltc E112: cannot locate 16 section(s):
ltc I455: requirement: 0xa0 bytes of ROM area in space mpe:vtc:linear
amk E452: ["makefile" 110/0] target 'RTOS_BSW.elf' returned exit code 1
amk E451: make stopped
ltc I456: section type: group restriction - ordered
ltc I457: .text.traptab0.trapvec.000 (23583) (0xa bytes)
ltc I457: .text.traptab0.trapvec.000 (23791) (0xa bytes)
ltc I457: .text.traptab0.trapvec.001 (23587) (0xa bytes)
ltc I457: .text.traptab0.trapvec.001 (23803) (0xa bytes)
ltc I457: .text.traptab0.trapvec.002 (23591) (0xa bytes)
ltc I457: .text.traptab0.trapvec.002 (23827) (0xa bytes)
ltc I457: .text.traptab0.trapvec.003 (23595) (0xa bytes)
ltc I457: .text.traptab0.trapvec.003 (23779) (0xa bytes)
ltc I457: .text.traptab0.trapvec.004 (23599) (0xa bytes)
ltc I457: .text.traptab0.trapvec.004 (23815) (0xa bytes)
ltc I453: ... (6 more I457 messages suppressed)
ltc E112: cannot locate 16 section(s):
ltc I455: requirement: 0xa0 bytes of ROM area in space mpe:vtc:linear
ltc I456: section type: group restriction - ordered
ltc I457: .text.traptab1.trapvec.000 (23584) (0xa bytes)
ltc I457: .text.traptab1.trapvec.000 (23792) (0xa bytes)
ltc I457: .text.traptab1.trapvec.001 (23588) (0xa bytes)
ltc I457: .text.traptab1.trapvec.001 (23804) (0xa bytes)
ltc I457: .text.traptab1.trapvec.002 (23592) (0xa bytes)
ltc I457: .text.traptab1.trapvec.002 (23828) (0xa bytes)
ltc I457: .text.traptab1.trapvec.003 (23596) (0xa bytes)
ltc I457: .text.traptab1.trapvec.003 (23780) (0xa bytes)
ltc I457: .text.traptab1.trapvec.004 (23600) (0xa bytes)
ltc I457: .text.traptab1.trapvec.004 (23816) (0xa bytes)
ltc I453: ... (6 more I457 messages suppressed)
ltc E112: cannot locate 16 section(s):
ltc I455: requirement: 0xa0 bytes of ROM area in space mpe:vtc:linear
ltc I456: section type: group restriction - ordered
ltc I457: .text.traptab2.trapvec.000 (23585) (0xa bytes)
ltc I457: .text.traptab2.trapvec.000 (23793) (0xa bytes)
ltc I457: .text.traptab2.trapvec.001 (23589) (0xa bytes)
ltc I457: .text.traptab2.trapvec.001 (23805) (0xa bytes)
ltc I457: .text.traptab2.trapvec.002 (23593) (0xa bytes)
ltc I457: .text.traptab2.trapvec.002 (23829) (0xa bytes)
ltc I457: .text.traptab2.trapvec.003 (23597) (0xa bytes)
ltc I457: .text.traptab2.trapvec.003 (23781) (0xa bytes)
ltc I457: .text.traptab2.trapvec.004 (23601) (0xa bytes)
ltc I457: .text.traptab2.trapvec.004 (23817) (0xa bytes)
ltc I453: ... (6 more I457 messages suppressed)

Kindly can someone shed your thoughts on it , please. Kindly do not hesitate to ask me for more information.

Many thanks,
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User13836
Level 6
Level 6
50 likes received 50 solutions authored 100 sign-ins
Hello Deepak,

thanks for the update. I suppose the following known issue is causing the trouble:

TCVX-44101 Definition of a trap service routine causes a linker error even if the default handler is disabled

DESCRIPTION
The program listed below has a trap service routine defined in the application source code. When it is built with default settings for AURIX 1G (TC27x) or AURIX 2G (TC39x-B), the linker throws an error due to duplicate vector entries, even if the corresponding start-up code setting "Class 7: Non-Maskable interrupt" for core 0 is disabled - macro __RESOLVE_TRAP_7 in cstart.h defined to 0.

Sample code :

int main(void)
{
printf( "Hello world\n" );
}

/* This definition will trigger error for duplicate Trap Vectors
* if not all trap functions for all cores are disabled in the
* startup configuration
* */

void __trap( 7 ) WDT_NMI_TSR( void )
{
while(1) __nop();
}

linker error:

ltc E112: cannot locate 9 section(s):
ltc I455: requirement: 0x5a bytes of ROM area in space mpe:vtc:linear
amk E452: ["makefile" 22/0] target 'TC397XA_Sim_Hello.elf' returned exit code 1
ltc I456: section type: group restriction - ordered
amk E451: make stopped
ltc I457: .text.traptab0.trapvec.000 (412) (0xa bytes)
ltc I457: .text.traptab0.trapvec.001 (424) (0xa bytes)
ltc I457: .text.traptab0.trapvec.002 (448) (0xa bytes)
ltc I457: .text.traptab0.trapvec.003 (400) (0xa bytes)
ltc I457: .text.traptab0.trapvec.004 (436) (0xa bytes)
ltc I457: .text.traptab0.trapvec.005 (388) (0xa bytes)
ltc I457: .text.traptab0.trapvec.006 (472) (0xa bytes)
ltc I457: .text.traptab0.trapvec.007 (345) (0xa bytes)
ltc I457: .text.traptab0.trapvec.007 (460) (0xa bytes)

MITIGATION
Disable each trap handler that will be defined in application code, for all cores, in C/C++->Startup Configuration. Define those handlers in application code for all cores (unless the trap does not need to be handled for certain cores).

Or add:

#pragma alias _trapnmi WDT_NMI_TSR

in the source file (or the equivalent for different traps and trap handlers).



Please verify if your application does use the default startup code included in the TASKING tools. I created a small use case which is based on the information you provided. Therein I can reproduce the locate errors. After I added the startup code sources and disabled the trap table references for all three cores in the cstart header files the error messages disappear.

You can build the use case using the following command prompt invocation:

cctc file_1.c cstart.c cstart_tc1.c cstart_tc2.c -Ctc27x -t -v -o result.elf -Wl-DTRAPTAB=(INTTAB-0x300)

After you added the path to the \ctc\bin subfolder of your TriCore tools installation folder to the PATH environment variable.

Best regards,
Ulrich

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User13836
Level 6
Level 6
50 likes received 50 solutions authored 100 sign-ins
Hello!

For requests related to the commercial TASKING TriCore tools you can consider to use the TASKING tools support email address: support@tasking.com. This also allows to register you do enable the TASKING supportcenter usage.

About the behavior you noticed. Please let me know the value of the INTTAB macro. Maybe INTTAB - 0x100 is pointing to an address where no flash memory is available or this is occupied by other sections.

Also: Please note that the trap table sections for each core do have a 0x100 byte offset. The LSL file for the TC27x derivative includes the following entries:

#ifndef INTTAB
#define INTTAB 0xa00f0000 /* start address of interrupt table */
#endif
#ifndef TRAPTAB
#define TRAPTAB (INTTAB + 0x6000) /* start address of trap table */
#endif

#ifndef INTTAB0
#define INTTAB0 (INTTAB)
#endif
#ifndef INTTAB1
#define INTTAB1 (INTTAB0 + 0x2000)
#endif
#ifndef INTTAB2
#define INTTAB2 (INTTAB1 + 0x2000)
#endif

#ifndef TRAPTAB0
#define TRAPTAB0 (TRAPTAB)
#endif
#ifndef TRAPTAB1
#define TRAPTAB1 (TRAPTAB0 + 0x100)
#endif
#ifndef TRAPTAB2
#define TRAPTAB2 (TRAPTAB1 + 0x100)
#endif

So in order to have all three trap tables for all three TriCore CPUs included in a TC27x located before the interrupt table start address you need to use:

#define TRAPTAB (INTTAB - 0x300)

Or you need to modify the macros used in the LSL file to change the offset between the individual trap tables.

Best regards,
Ulrich Kloidt

TASKING tools support
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DSRnathan
Level 3
Level 3
50 sign-ins 25 replies posted 25 sign-ins
hello Ulrichk,
Thank you very much for the response. As you corectly mentioned the INITTAB 0xa00ff0000 is a default address from the TC27xd.lsl. This is a RTOS environment, the trap() qualifier function are defined for all the trap classes realted with the scheduler application. If I remove the trap function definitions, the build is successfull with the trap vector table locating in the default mentioned addresses + offset otherwise I am ending up getting this linker error. The application will not run and enter into a frozen state if I remove the below functions.
The defined __trap() are for eg.,

__trap( TRAP_CLASS_SYSCALL ) __vector_table( 0, 1, 2 ) void vSyscallTrapEntry( void ) // TRAP_CLASS_SYSCALL macro defined value for its class -6
{
/* We need to go to vSafeRTOSSVCHandler with a Jump, because a CALL would
* save another CSA, which would make this less efficient. */
__asm
(
" mov d4, d15 \n"
" ji %0 \n"
" rfe \n"
:: "a" ( vSafeRTOSSVCHandler )
: "d4", "d15"
);
}
/*---------------------------------------------------------------------------*/

__trap( TRAP_CLASS_MMU ) __vector_table( 0, 1, 2 ) void vMMUTrapEntry( void )
{
portUnsignedBaseType uxTin;

__asm( "mov %0,d15" : "=d" ( uxTin ) ); /* Put d15 in C variable uxTin. */

/* Read program counter address where fault occurred. */
__asm( "mov.d %0, a11": "=d" ( uxLastErrorInstructionAddress ) );

switch( uxTin )
{
case 1:
__debug(); /* VAF -- Virtual Address Fill */
break;

case 2:
__debug(); /* VAP -- Virtual Address Protection */
break;
}

prvVectorHold( TRAP_CLASS_MMU, uxTin );
}
/*---------------------------------------------------------------------------*/

__trap( TRAP_CLASS_IPT ) __vector_table( 0, 1, 2 ) void vInternalProtectionTrapEntry( void )
{
portUnsignedBaseType uxTin;

__asm( "mov %0,d15" : "=d" ( uxTin ) ); /* Put d15 in C variable uxTin. */

/* Store TIN. */
uxLastProtErrorId = uxTin;

/* Read program counter address where fault occurred. */
__asm( "mov.d %0, a11": "=d" ( uxLastErrorInstructionAddress ) );

switch( uxTin )
{
case TRAP_IPT_MPR: /* MPR -- MemProt: Read Access */
case TRAP_IPT_MPW: /* MPW -- MemProt: Write Access */
case TRAP_IPT_MPP: /* MPP -- MemProt: Peripheral Access */
case TRAP_IPT_MPN: /* MPN -- MemProt: Null Address */
/* Error on Read or Write access. */
uxLastErrorMask = ( portUnsignedBaseType ) __mfcr( CPU_DSTR );
uxLastErrorDataAddress = ( portUnsignedBaseType ) __mfcr( CPU_DEADD );
break;

case TRAP_IPT_PRIV: /* PRIV -- Privileged Instruction */
case TRAP_IPT_MPX: /* MPX -- MemProt: Execution Access */
/* Error on Execute access. */
/* The offending instruction is already saved in
* uxLastErrorInstructionAddress. */
break;

case TRAP_IPT_GRWP: /* GRPW -- Global Register Write Prot */
/* Error on Global register access. */
__debug();
break;

default:
/* Unknown TIN. */
__debug();
break;
}

prvVectorHold( TRAP_CLASS_IPT, uxTin );
}

I am looking for the missing bit here. Kindly shed your thoughts. I also tried the INTTAB - 0x300 and end up with the same error.

Kind regards,
Deepak
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User13836
Level 6
Level 6
50 likes received 50 solutions authored 100 sign-ins
Hello Deepak,

thanks for the update. I suppose the following known issue is causing the trouble:

TCVX-44101 Definition of a trap service routine causes a linker error even if the default handler is disabled

DESCRIPTION
The program listed below has a trap service routine defined in the application source code. When it is built with default settings for AURIX 1G (TC27x) or AURIX 2G (TC39x-B), the linker throws an error due to duplicate vector entries, even if the corresponding start-up code setting "Class 7: Non-Maskable interrupt" for core 0 is disabled - macro __RESOLVE_TRAP_7 in cstart.h defined to 0.

Sample code :

int main(void)
{
printf( "Hello world\n" );
}

/* This definition will trigger error for duplicate Trap Vectors
* if not all trap functions for all cores are disabled in the
* startup configuration
* */

void __trap( 7 ) WDT_NMI_TSR( void )
{
while(1) __nop();
}

linker error:

ltc E112: cannot locate 9 section(s):
ltc I455: requirement: 0x5a bytes of ROM area in space mpe:vtc:linear
amk E452: ["makefile" 22/0] target 'TC397XA_Sim_Hello.elf' returned exit code 1
ltc I456: section type: group restriction - ordered
amk E451: make stopped
ltc I457: .text.traptab0.trapvec.000 (412) (0xa bytes)
ltc I457: .text.traptab0.trapvec.001 (424) (0xa bytes)
ltc I457: .text.traptab0.trapvec.002 (448) (0xa bytes)
ltc I457: .text.traptab0.trapvec.003 (400) (0xa bytes)
ltc I457: .text.traptab0.trapvec.004 (436) (0xa bytes)
ltc I457: .text.traptab0.trapvec.005 (388) (0xa bytes)
ltc I457: .text.traptab0.trapvec.006 (472) (0xa bytes)
ltc I457: .text.traptab0.trapvec.007 (345) (0xa bytes)
ltc I457: .text.traptab0.trapvec.007 (460) (0xa bytes)

MITIGATION
Disable each trap handler that will be defined in application code, for all cores, in C/C++->Startup Configuration. Define those handlers in application code for all cores (unless the trap does not need to be handled for certain cores).

Or add:

#pragma alias _trapnmi WDT_NMI_TSR

in the source file (or the equivalent for different traps and trap handlers).



Please verify if your application does use the default startup code included in the TASKING tools. I created a small use case which is based on the information you provided. Therein I can reproduce the locate errors. After I added the startup code sources and disabled the trap table references for all three cores in the cstart header files the error messages disappear.

You can build the use case using the following command prompt invocation:

cctc file_1.c cstart.c cstart_tc1.c cstart_tc2.c -Ctc27x -t -v -o result.elf -Wl-DTRAPTAB=(INTTAB-0x300)

After you added the path to the \ctc\bin subfolder of your TriCore tools installation folder to the PATH environment variable.

Best regards,
Ulrich
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DSRnathan
Level 3
Level 3
50 sign-ins 25 replies posted 25 sign-ins
Hello Ulrich,
Thank you for the explanation and the issue is resolved. The content discussion was very much useful.

Kind Regards,
Deepak
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