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Thread: How can I be sure that the transmission error bit TER is safely detected?

  1. #1
    New Member New Member gustavo is on a distinguished road
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    Nov 2020

    How can I be sure that the transmission error bit TER is safely detected?

    I'm concerned about an identical identification of a TER message with a read back of a register command.
    Could there be a mix match between STD Diagnosis and Read Commands?
    What to do to reliably detect a TER case?

  2. #2

    Infineon Employee
    Infineon Employee
    LED-Peter is on a distinguished road
    Join Date
    Nov 2020
    Munich, Germany
    There are two ways to check if a transmission error has happened:

    1) Monitor the TER flag on the SO pin in the time window between the chip select assertion and the first clock rising edge, please refer on figure 28 of the TLD5501-2QV datasheet. Usually this solution requires extra HW (i.e. one extra GPIO).
    2) Monitor the TER bit in the standard diagnosis. You can distinguish the standard diagnosis frame from another frame response by checking the frame MSB. In a standard diagnosis frame the MSB is set to 0. In case of a response after a reading request the TLD5501-2QV is setting the MSB of the frame to 1.

    Find the datasheet and more information on https://www.infineon.com/cms/en/prod...x/tld5501-2qv/

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