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Thread: TC223 PFLASH Programming

  1. #21
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    Infineon Employee
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    Darren Galpin is on a distinguished road
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    I don't know TriCore assembler at all well. but the highlighted command in yellow appears to have the same address offset at the SVLCX command in the lower snapshot. It looks like the controller is having an issue trying to execute the trap handler and saving the context. Where is it saving the context to?
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  2. #22
    Beginner Beginner alexander.bil is on a distinguished road
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    Hello Darren,

    unfortunately I do not know how to answer your question. Could you explain in more detail what information is required?
    I have checked the D15 Register which contains the TIN. It says 4 which is an Memory Protection Execute. Is there some protection of the pflash when erasing it? Should I include some delay? Because when I step through with the debugger I do not encounter such problems.

  3. #23
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    Darren Galpin is on a distinguished road
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    When erasing a flash, the busy bit for the flash bank is set in the status register, and any access to the bank being erased will error. Hence the recommended sequence when erasing a bank is to wait for the busy to go high, then wait for it to go low, and then you can read the erased flash without an issue.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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