Nov 16, 2020
10:35 AM
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Nov 16, 2020
10:35 AM
Hello Support,
Shown below the CPU Access Latency Table from Aurix 2G User Manual.
Where do I obtain the "Module Wait State" values for each Peripheral Module as present within TC387 device?
Any snippet from the User Manual where it is already mentioned, if you can provide then I can understand better the total access latency for each modules on the Bus.
The footnote 2 mentions that for each peripheral module, it is configurable.
I am assuming it is configurable during RTL design phase and not end-user modifiable.
Best Regards
Shown below the CPU Access Latency Table from Aurix 2G User Manual.
Where do I obtain the "Module Wait State" values for each Peripheral Module as present within TC387 device?
Any snippet from the User Manual where it is already mentioned, if you can provide then I can understand better the total access latency for each modules on the Bus.
The footnote 2 mentions that for each peripheral module, it is configurable.
I am assuming it is configurable during RTL design phase and not end-user modifiable.
Best Regards
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- IFX
1 Reply
Nov 16, 2020
02:10 PM
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Nov 16, 2020
02:10 PM
STM, PSI5, PSI5S, HSSL, HSCT: 1 additional wait state
DMA, ERAY, I2C: 2
GETH - 4
EVADC-8
EDSADC -8
CONVCTRL-8
MTU(SSH) - 9
GTM - 9
PMS - 8
Peripherals not listed above: 1 SPB wait state
DMA, ERAY, I2C: 2
GETH - 4
EVADC-8
EDSADC -8
CONVCTRL-8
MTU(SSH) - 9
GTM - 9
PMS - 8
Peripherals not listed above: 1 SPB wait state