Nov 12, 2020
08:07 PM
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Nov 12, 2020
08:07 PM
Can you please let me know what is the worst-case tolerance/deviation of Peripheral PLL (fpll1) of AURIX TC377TP ?
Source clock for CAN Baud Rate generation (fASYN/fMCAN) is selectable between Peripheral PLL (fpll1) and OSC_XTAL (fOSC0).
CAN ISO/J1939 physical layer requirements indicates "tolerance on resulting bit time should be less than +/- 0.05% over the applicable temperature range and life of the device"
So I wondering if I can meet these requirements if Peripheral PLL (fpll1) is the chosen as the source. I went through the data sheet, but I could not find this, Any thoughts ?
Source clock for CAN Baud Rate generation (fASYN/fMCAN) is selectable between Peripheral PLL (fpll1) and OSC_XTAL (fOSC0).
CAN ISO/J1939 physical layer requirements indicates "tolerance on resulting bit time should be less than +/- 0.05% over the applicable temperature range and life of the device"
So I wondering if I can meet these requirements if Peripheral PLL (fpll1) is the chosen as the source. I went through the data sheet, but I could not find this, Any thoughts ?
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- aurix tc37x
- fpll
- IFX
4 Replies
Nov 13, 2020
09:42 AM
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Nov 13, 2020
09:42 AM
Check out Table 3-37 PLL Peripheral in the datasheet.
"Peak accumulated jitter" is +/- 700 ps. The accumulated jitter over a single bit time interval (e.g., 500 ns @ 2 Mbps) is a little less than that - see application note AP32390 for a discussion of short-term and long-term jitter.
Of course, that needs to be added to the variation of the external oscillator, which is typically something like 300 ppm.
"Peak accumulated jitter" is +/- 700 ps. The accumulated jitter over a single bit time interval (e.g., 500 ns @ 2 Mbps) is a little less than that - see application note AP32390 for a discussion of short-term and long-term jitter.
Of course, that needs to be added to the variation of the external oscillator, which is typically something like 300 ppm.
Nov 22, 2020
02:29 PM
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Nov 22, 2020
02:29 PM
UC_wrangler wrote:
Check out Table 3-37 PLL Peripheral in the datasheet.
"Peak accumulated jitter" is +/- 700 ps. The accumulated jitter over a single bit time interval (e.g., 500 ns @ 2 Mbps) is a little less than that - see application note AP32390 for a discussion of short-term and long-term jitter.
Of course, that needs to be added to the variation of the external oscillator, which is typically something like 300 ppm.
I went through AP32390. From AP32390 it looks like using PLL as clock source for CAN Baud Rate generation is not a good idea.
Is my understanding correct or am I missing something ?
In my past experience in using TC2xx devices, we were recommended to not use PLL as clock source for CAN. I am assuming this is true even for TC3xx devices. Any thoughts ?
Nov 22, 2020
08:55 PM
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Nov 22, 2020
08:55 PM
Usually, the TC2xx FlexRay PLL or TC3xx Peripheral PLL is close enough for 1 Mbps and slower, but not for CAN FD. Each OEMs has strict requirements that dictate the CAN clock source, and sometimes even resonator vs. crystal.
Nov 23, 2020
08:36 AM
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Nov 23, 2020
08:36 AM
UC_wrangler wrote:
Usually, the TC2xx FlexRay PLL or TC3xx Peripheral PLL is close enough for 1 Mbps and slower, but not for CAN FD. Each OEMs has strict requirements that dictate the CAN clock source, and sometimes even resonator vs. crystal.
Thank you. Appreciate your help