Nov 03, 2020
09:12 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 03, 2020
09:12 AM
Hello, I have a problem with TC3xx EVADC.
When i enter to the queue multiple conversions of the same channel, only the last conversion of this channel is done,
and the conversions of the others channels are ok.
I illustrate that with the following example:
Where is the problem ?
//initialize the EVADC channel:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
adcChannelConfig[1].reference = (IfxEvadc_ChannelReference)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//Result is ok:
// EVADC_G8RES0 has Ch7 result
// EVADC_G8RES1 has Ch6 result
//******************************************************************
//initialize the EVADC channels:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[2], &g_adcGroup);
adcChannelConfig[2].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[2].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[2], &adcChannelConfig[2]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[2], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//BAD Result :
// EVADC_G8RES0 = 0
// EVADC_G8RES1 has Ch6 result
// EVADC_G8RES2 has Ch7 result
//*******************************************************************
//initialize the EVADC channels:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[2], &g_adcGroup);
adcChannelConfig[2].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[2].resultRegister = (IfxEvadc_ChannelResult)(2);
IfxEvadc_Adc_initChannel(&g_adcChannel[2], &adcChannelConfig[2]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[3], &g_adcGroup);
adcChannelConfig[3].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[3].resultRegister = (IfxEvadc_ChannelResult)(3);
IfxEvadc_Adc_initChannel(&g_adcChannel[3], &adcChannelConfig[3]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[2], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[3], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//BAD Result :
// EVADC_G8RES0 = 0
// EVADC_G8RES1 has Ch6 result
// EVADC_G8RES2 = 0
// EVADC_G8RES3 has Ch7 result
Thank you for your answer.
When i enter to the queue multiple conversions of the same channel, only the last conversion of this channel is done,
and the conversions of the others channels are ok.
I illustrate that with the following example:
Where is the problem ?
//initialize the EVADC channel:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
adcChannelConfig[1].reference = (IfxEvadc_ChannelReference)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//Result is ok:
// EVADC_G8RES0 has Ch7 result
// EVADC_G8RES1 has Ch6 result
//******************************************************************
//initialize the EVADC channels:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[2], &g_adcGroup);
adcChannelConfig[2].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[2].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[2], &adcChannelConfig[2]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[2], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//BAD Result :
// EVADC_G8RES0 = 0
// EVADC_G8RES1 has Ch6 result
// EVADC_G8RES2 has Ch7 result
//*******************************************************************
//initialize the EVADC channels:
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[0], &g_adcGroup);
adcChannelConfig[0].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[0].resultRegister = (IfxEvadc_ChannelResult)(0);
IfxEvadc_Adc_initChannel(&g_adcChannel[0], &adcChannelConfig[0]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[1], &g_adcGroup);
adcChannelConfig[1].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch6 Gr8
adcChannelConfig[1].resultRegister = (IfxEvadc_ChannelResult)(1);
IfxEvadc_Adc_initChannel(&g_adcChannel[1], &adcChannelConfig[1]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[2], &g_adcGroup);
adcChannelConfig[2].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[2].resultRegister = (IfxEvadc_ChannelResult)(2);
IfxEvadc_Adc_initChannel(&g_adcChannel[2], &adcChannelConfig[2]);
IfxEvadc_Adc_initChannelConfig(&adcChannelConfig[3], &g_adcGroup);
adcChannelConfig[3].channelId = (IfxEvadc_ChannelId)(AN0SB_CHID); // ch7 Gr8
adcChannelConfig[3].resultRegister = (IfxEvadc_ChannelResult)(3);
IfxEvadc_Adc_initChannel(&g_adcChannel[3], &adcChannelConfig[3]);
//Queue filling
IfxEvadc_Adc_addToQueue(&g_adcChannel[0], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[1], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[2], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
IfxEvadc_Adc_addToQueue(&g_adcChannel[3], IfxEvadc_RequestSource_queue0, IFXEVADC_QUEUE_REFILL);
//BAD Result :
// EVADC_G8RES0 = 0
// EVADC_G8RES1 has Ch6 result
// EVADC_G8RES2 = 0
// EVADC_G8RES3 has Ch7 result
Thank you for your answer.
- Tags:
- IFX
5 Replies
Nov 03, 2020
10:45 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 03, 2020
10:45 AM
Nov 04, 2020
02:23 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 04, 2020
02:23 AM
Thank you for your answer,
it is very difficult to understand this microcontroller and to approach its programation without having access to all its information.
However, the solution you give doesn't work...
EVADC_G8CHCTR7.B.RESREG = 0; make a SW TRAP error interrupt
EVADC_G8QCTRLx.B.SRCRESREG = y ; has no visible effect and no effect on the EVADC_G8RESx results (x = 0,1 or 2)
EVADC_G8QCTRLx.B.SRCRESREG = y ; makes an error compilation when x > 2
It’s very frustrating because it says in the datasheet that "multiple conversions of the same channel within a sequence are supported"...
it is very difficult to understand this microcontroller and to approach its programation without having access to all its information.
However, the solution you give doesn't work...
EVADC_G8CHCTR7.B.RESREG = 0; make a SW TRAP error interrupt
EVADC_G8QCTRLx.B.SRCRESREG = y ; has no visible effect and no effect on the EVADC_G8RESx results (x = 0,1 or 2)
EVADC_G8QCTRLx.B.SRCRESREG = y ; makes an error compilation when x > 2
It’s very frustrating because it says in the datasheet that "multiple conversions of the same channel within a sequence are supported"...
Nov 04, 2020
05:47 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 04, 2020
05:47 AM
Sorry, my previous post wasn't correct - there's just one QCTRL register per queued source, not one for each channel.
Converting multiple instances of the same channel is usually handled by having the conversion result generate a service request, and then DMA copies every conversion result for that queued source into a RAM buffer.
I take that to mean you don't have the User Manual part 1 and part 2? Do you have a MyICP account?
You'll definitely need the User Manual to understand how to route the EVADC result service request into DMA.
Converting multiple instances of the same channel is usually handled by having the conversion result generate a service request, and then DMA copies every conversion result for that queued source into a RAM buffer.
it is very difficult to understand this microcontroller and to approach its programation without having access to all its information.
I take that to mean you don't have the User Manual part 1 and part 2? Do you have a MyICP account?
You'll definitely need the User Manual to understand how to route the EVADC result service request into DMA.
Nov 04, 2020
06:54 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 04, 2020
06:54 AM
Hello,
No, I don't have the User Manual part 1 and part 2, and I don't have access to aurix documentation in MyICP account. They don't give me access because i don't have a "corporate email or an email with a company that is in their NDA list".
I will ask one more time, we never know...
Thank you for your help.
No, I don't have the User Manual part 1 and part 2, and I don't have access to aurix documentation in MyICP account. They don't give me access because i don't have a "corporate email or an email with a company that is in their NDA list".
I will ask one more time, we never know...
Thank you for your help.
Nov 04, 2020
01:43 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nov 04, 2020
01:43 PM
Ah, but since the devices are in production now, the flood gates have been opened:
User Manual Part 1
https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v01_00-EN.pdf?fileId=5546d462712...
Part 2
https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v01_00-EN.pdf?fileId=5546d462712...
User Manual Part 1
https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v01_00-EN.pdf?fileId=5546d462712...
Part 2
https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v01_00-EN.pdf?fileId=5546d462712...