Oct 27, 2020
07:17 AM
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Oct 27, 2020
07:17 AM
My program puts data into FIFO of USIC. But this data is not immediately transferred to transmitter buffer (USIC.TBUF). Transfer to USIC.TBUF is carried out only by a signal from timer.
Everything works correctly as I want. Except for one little thing: I connected this timer signal (which starts copying USIC.FIFO -> USIC.TBUF) to an external pin. And I see that beginning of start bit (on USIC.TXD) is delayed by ~0.25mcs relative to timer signal.
Why does this delay occur??? I expected edge of start bit will happen synchronously with edge of timer signal.
Clock frequency of timer and USIC == 144MHz. Baudrate of USIC == 1Mbod.
Everything works correctly as I want. Except for one little thing: I connected this timer signal (which starts copying USIC.FIFO -> USIC.TBUF) to an external pin. And I see that beginning of start bit (on USIC.TXD) is delayed by ~0.25mcs relative to timer signal.
Why does this delay occur??? I expected edge of start bit will happen synchronously with edge of timer signal.
Clock frequency of timer and USIC == 144MHz. Baudrate of USIC == 1Mbod.
- Tags:
- IFX
- usic.timer
3 Replies
Oct 28, 2020
02:24 AM
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Oct 28, 2020
02:24 AM
Hi,
Are you using the transfer trigger logic as depicted below?
Regards,
Jesus
Are you using the transfer trigger logic as depicted below?
Regards,
Jesus
Oct 28, 2020
09:27 AM
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Oct 28, 2020
09:27 AM
jferreira wrote:
Are you using the transfer trigger logic as depicted below?
Yes. Talk about USIC0.CH1 + CCU80.SR1.
USIC.SCTR = 1 << 1 | 1 << 8 | 24 - 1 << 16 | 16 - 1 << 24;
USIC.TCSR = 1 << 0 | 1 << 8 | 1 << 10 | 1 << 12;
USIC.DXCR[2] = 1 << 10 | USIC0_CH1.DX2F;
I am programming two slices of CCU80 to generate two request CCU80.SR1 (the second request CCU80.SR1 occurs 5 μs after first CCU80.SR1). These two CCU80.SR1 are copying the full 24-bit word from FIFO to TBUF USIC.
And I expected the start of the start bit on TXD to coincide with the first SR. But inexplicably TXD is always delayed by about 0.25μs relative to the edge of first CCU80.SR1.
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Oct 30, 2020
08:24 AM
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Oct 30, 2020
08:24 AM