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Thread: TC299 Multicore __private aurix studio

  1. #1
    Beginner Beginner Gaziom is on a distinguished road
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    TC299 Multicore __private aurix studio

    Hi,
    I am working with a triboard TC299 v1.1 and Aurix Developement Studio.

    I try to use the __privateN argument to block a function call form an other core but I keep getting cpu trap ( class4, tin1).

    Could this be due to the fact that the chip on the tc299 is a sak-tc299tf-128 f300n-bc-es ?

    I tried to use the "pragma code_core_association privateN" but i still get cpu trap (class 4, tin3).

    As someone already used the __private tags ?

    Regards,
    Octave

  2. #2
    Advanced Advanced UC_wrangler will become famous soon enough
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    Quote Originally Posted by Gaziom View Post
    I try to use the __privateN argument to block a function call form an other core
    __private<n> is generally used to put a function in one core's PSPR (Program Scratch Pad) memory. It doesn't prevent another core from calling the function - but if another core does, it will likely encounter an illegal instruction, because the function isn't in that core's PSPR.

    What is it you're trying to do? If you're trying to prevent access to certain sections of code, most application use the CPU Memory Protection Unit.

  3. #3
    Beginner Beginner Gaziom is on a distinguished road
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    Hi,
    thanks for the fast reply.

    Yes, I want to prevent acess to certain sections of code from other core but I can't find a lot of documentation on CPU Memory Protection Unit.

    And when I use __private2 on a function I call with core2 I still get traps... Is this normal?

  4. #4
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    Quote Originally Posted by Gaziom View Post
    And when I use __private2 on a function I call with core2 I still get traps... Is this normal?
    No, it's not - but it could be that your linker file is not handling the PSPR copy correctly.

    Here's a ilttle example that does both CPU Memory Protection and Safety Memory Protection.
    Code:
    /*****************************************************
     *
     * mpu_demo.c
     *
     * Description : Demonstrate Memory Protection Unit
     *
     */
    
    #include "IfxCpu_reg.h"
    #include "IfxScu_reg.h"
    #include "IfxSmu_reg.h"
    
    const char s[] = "abcdefghijklmno";
    
    // Memory Protection for data must be aligned to 8-byte intervals
    #pragma align 8
    volatile unsigned long data1[8];
    volatile unsigned long data2[8];
    volatile unsigned long data3[8];
    volatile unsigned long x;
    char *bump;
    volatile unsigned long *ulptr;
    int syscon;
    long long *ll;
    
    volatile unsigned long nmi_count;
    
    /*
    void __trap( 7 ) nmi_handler( void )
    {
    	for( ;; )
    	{
    		++nmi_count;
    	}
    }
    */
    
    int main(void)
    {
    #if 0
        __mtcr( CPU_DPR0_L, (int) 0x70000000 );
        __mtcr( CPU_DPR0_U, (int) data2 );
        __mtcr( CPU_DPR1_L, (int) data3 );
        __mtcr( CPU_DPR1_U, (int) 0x7002E000 );
        __mtcr( CPU_DPRE0, 3 );         // enable read protection for DPR0
        __mtcr( CPU_DPWE0, 3 );         // enable write protection for DPR0
        __mtcr( CPU_CPR0_L, (int) 0x80000000 );
        __mtcr( CPU_CPR0_U, (int) 0x80200000 );
        __mtcr( CPU_CPR1_L, (int) 0xA0000000 );
        __mtcr( CPU_CPR1_U, (int) 0xA0200000 );
        __mtcr( CPU_CPXE0, 3 );         // enable code execution access to range 0 and 1
      syscon = __mfcr( CPU_SYSCON );
      syscon |= 2;
      __mtcr( CPU_SYSCON, syscon );		// SYSCON.PROTEN=1
    
    //  x = data2[0];                   // now this causes a TRAP (0x70000020 is blocked)
      bump = (char *) data2;
      bump -= 2;                        // But accessing the word that's halfway out doesn't (0x70000026-0x70000029)
      ulptr = (unsigned long *) bump;
      x = *ulptr;
    
      ll = (long long *) bump;          // And accessing the double longword (8 bytes) that's halfway out doesn't either (0x70000026-0x7000002D)
      *ll = 7;
    #endif
        // Safety Memory Protection demo
        // - Safety Memory Protection prevents writes to CPU memory from bus masters:
        // -- RGNUAx and RGNLAx define an upper and lower memory limit (32-byte granularity).
        // -- RGNACCENAx defines which bus masters can write to each range.
        //      see TC29x User Manual page 219: Table 2-15 On Chip Bus Master TAG Assignments
        //        bit 0: CPU0 DMI.Nonsafe
        //        bit 1: CPU0 DMI.Safe
        //        bit 2: CPU1 DMI.Nonsafe
        //        bit 3: CPU1 DMI.Safe
        //        bit 4: CPU2 DMI.Nonsafe
        //        bit 5: CPU2 DMI.Safe
        //        bit 6: DMA resource partition 0
        //        bit 7: DMA resource partition 1
        //        bit 8: DMA resource partition 2
        //        bit 9: DMA resource partition 3
        //        bit 10: Cerberus (debug)
        //        bit 11: HSSL
        //        bit 12: Ethernet
        //        bit 13: HSM
        //        bit 16: CPU0.PMI
        //        bit 17: CPU1.PMI
        //        bit 18: CPU2.PMI
        //        bit 24: DAM
        //        bit 28: IOC32
        //        bit 29: EMEM
        //        bit 30: CIF
        //
        // Note that the 8 ranges are logical-or'ed together; i.e., if one of the ranges
        // allows writing, the memory write is permitted.
    
        // Safety Memory Protection demo 1: prevent CPU0 from writing to its own PSPR @ 0x70101000.
        // - Note that when a CPU writes to its own PSPR, its DMI goes across the SRI bus.
        //
      	_safety_endinit_clear();
    	CPU0_SPROT_RGNLA0.U = 0x00000000;        // Lower limit: 0
    	CPU0_SPROT_RGNUA0.U = 0x70101000;        // Upper limit: PSPR0 @ 0x70100FFF
    	CPU0_SPROT_RGNACCENA0.U = 0x71073FFF;    // full access by all TC2xx bus masters
    							// 0111 0001 0000 0111 0011 1111 1111 1111
    
    
    	CPU0_SPROT_RGNLA1.U = 0x70101000;	     // Lower limit: PSPR0 @ 0x70101000
    	CPU0_SPROT_RGNUA1.U = 0x70101000;        // Upper limit: PSPR0 @ 0x7010101F
    	CPU0_SPROT_RGNACCENA1.U = 0x71023FCC;    // Prevent CPU0.DMI/PMI and CPU2.DMI/PMI (allow all others)
    							// 0111 0001 0000 0010 0011 1111 1100 1100
    
    	CPU0_SPROT_RGNLA2.U = 0x70101020;
    	CPU0_SPROT_RGNUA2.U = 0xFFFFFFFF;
    	CPU0_SPROT_RGNACCENA2.U = 0x71073FFF;    // full access by all TC2xx bus masters
    							// 0111 0001 0000 0111 0011 1111 1111 1111
    
    	// By default, all sets are wide open, so you need to disable the sets that are not used
    	CPU0_SPROT_RGNACCENA3.U = 0x0;           // prevent access by all bus masters
    	CPU0_SPROT_RGNACCENA4.U = 0x0;           // prevent access by all bus masters
    	CPU0_SPROT_RGNACCENA5.U = 0x0;           // prevent access by all bus masters
    	CPU0_SPROT_RGNACCENA6.U = 0x0;           // prevent access by all bus masters
    	CPU0_SPROT_RGNACCENA7.U = 0x0;           // prevent access by all bus masters
    
    	_safety_endinit_set();
    
    	_safety_endinit_clear();		// SMU registers are safety endinit protected
    	SMU_KEYS.U = 0xBC;				// CFGLCK=BC: unlock SMU configuration registers
    
    	SMU_AG0FSP.U = 0x0002;    	// enable CPU0 Bus-level Memory Protection Unit
    
    	// set all the Memory Protection Alarm SMU Alarm Configuration bits to 101b (SMU_NMI)
    	SMU_AG0CF0.U = 0x0002;    	// bit 0 of SMU Alarm configuration for alarm group 0
    	SMU_AG0CF1.U = 0x0000;    	// bit 1 of SMU Alarm configuration for alarm group 0
    	SMU_AG0CF2.U = 0x0002;    	// bit 2 of SMU Alarm configuration for alarm group 0
    
    	SMU_KEYS.U = 0;				// lock SMU configuration registers
    
    	_safety_endinit_set();		// end SMU configuration - safety endinit protected
    
    	_endinit_clear();			// SCU NMI trap configuration is endinit protected
    	SCU_TRAPDIS.B.SMUT = 0;      // enable SMU NMI trap generation
    	_endinit_set();
    
    	// Here the SMU is in the START state
    	// Deactivate the fault output with SMU_ReleaseFSP
    	//
    	SMU_CMD.U = 0x2;				// ARG=0, CMD=2: SMU_ReleaseFSP(0)
    
    	// The SMU_Start command causes a transition from START to RUN
    	//
    	SMU_CMD.U = 0;    			// ARG=0, CMD=0: SMU_Start(0)
    	for( int i=0; i<10000000; i++ ) {}	// kill some time
    
    
    	// Setting this address will not trigger Safety Memory Protection
    	// because it's defined in RGN0
    	*((unsigned long *) 0x70100FE0) = 0xFFFFFFFF;
    
    	// Safety Memory Protection will now cause an NMI from the SMU
    	*((unsigned long *) 0x70101000) = 0xFFFFFFFF;
    
      for( ;; )
      {
      }
    }

  5. #5
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    Quote Originally Posted by Gaziom View Post
    Hi,
    thanks for the fast reply.

    Yes, I want to prevent acess to certain sections of code from other core but I can't find a lot of documentation on CPU Memory Protection Unit.

    And when I use __private2 on a function I call with core2 I still get traps... Is this normal?
    Hello Gaziom,

    Here you can find a code example showing how to use the Memory Protection Unit: MPU_Memory_Protection_1_KIT_TC297_TFT (it can also be dowloaded from the AURIX Development Studio using Import..>Infineon )
    It also comes with a nice and detailed tutorial: MPU_Memory_Protection_1 tutorial.

    hope it helps,
    teoBits
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  6. #6
    Beginner Beginner Gaziom is on a distinguished road
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    Thank you, both of you.

    I will do some testing with the MPU and SMP.

  7. #7
    Beginner Beginner Gaziom is on a distinguished road
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    Hi again,

    I have an other question: is it possible to set different protection set on each cores ? for exemple core 0 use protection set 1, core use protection set 2 and core 2 use protection set 3.

    Or should I use the cpu safety protection region access as discribed in UC_Wrangler example ?

    Regards, Octave

  8. #8
    Advanced Advanced UC_wrangler will become famous soon enough
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    It's not only possible, it's mandatory: each core has its own set of Memory Protection and Safety Memory Protection registers.

    The Memory Protection Unit limits what ranges that particular CPU is allowed to access.

    Safety Memory Protection limits what other bus masters (other CPUs, DMA, Ethernet, and the HSM) are allowed to access in each CPU.
    Last edited by UC_wrangler; Oct 22nd, 2020 at 07:10 AM.

  9. #9
    Beginner Beginner Gaziom is on a distinguished road
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    thank you very much for the fast reply =)

    i understood more on this with your example and second reply than hours of reading the many infineon PDFs...

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