Oct 02, 2020
01:36 AM
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Oct 02, 2020
01:36 AM
Hi,
I believe there is an "error" in the HW_EepromReload() function in the xmc_eschw.c generated/template code of the ECAT_SSC app.
In HW_EepromReload(), EEPROMReg is initialized to 0, and never updated with the value of ESC_EEPROM_CONTROL_OFFSET.
I does some and-ing with a couple of masks which makes no sense as it is 0.
Then it updates ESC_EEPROM_CONTROL_OFFSET with it's value which is 0.
I hope I have overlooked something.
I have no idea of the implications but just clearing a register seems wrong. I believe a change like the following should be made:
UINT16 EEPROMReg = 0U; /* Regvalue 0x502 - 0x5003 */
+HW_EscReadWord(EEPROMReg,ESC_EEPROM_CONTROL_OFFSET);
UINT32 cmd = (uint32_t)EEPROMReg & (uint32_t)ESC_EEPROM_CMD_MASK;
Just like it is done in the loop.
I see that ecatappl.c, generated by SSC Tool, does exactly this and handles the case where ESC_EEPROM_CONTROL_OFFSET bit 6 is set, which in your code is cleared.
Dave Version: 4.4.2, ECAT_SSC v4_0_26
Hope someone can confirm this so I can make the changes manually.
Best regards Mathias
I believe there is an "error" in the HW_EepromReload() function in the xmc_eschw.c generated/template code of the ECAT_SSC app.
In HW_EepromReload(), EEPROMReg is initialized to 0, and never updated with the value of ESC_EEPROM_CONTROL_OFFSET.
I does some and-ing with a couple of masks which makes no sense as it is 0.
Then it updates ESC_EEPROM_CONTROL_OFFSET with it's value which is 0.
I hope I have overlooked something.
I have no idea of the implications but just clearing a register seems wrong. I believe a change like the following should be made:
UINT16 EEPROMReg = 0U; /* Regvalue 0x502 - 0x5003 */
+HW_EscReadWord(EEPROMReg,ESC_EEPROM_CONTROL_OFFSET);
UINT32 cmd = (uint32_t)EEPROMReg & (uint32_t)ESC_EEPROM_CMD_MASK;
Just like it is done in the loop.
I see that ecatappl.c, generated by SSC Tool, does exactly this and handles the case where ESC_EEPROM_CONTROL_OFFSET bit 6 is set, which in your code is cleared.
Dave Version: 4.4.2, ECAT_SSC v4_0_26
Hope someone can confirm this so I can make the changes manually.
Best regards Mathias
1 Reply
Oct 13, 2020
05:45 AM
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Oct 13, 2020
05:45 AM
Hi Mathias,
please check the Register EEPROM Control/Status and the read-only bitfield BYTES inside reference manual:
Supported number of EEPROM read bytes
0B 4 Bytes
1B 8 Bytes
For XMC48 this bitfield always reads back 1B.
Hardware implementation is fixed to 8Bytes. This setting cannot be changed by software.
With SSC5.12 the HW_EepromReload is only getting called inside void EEPROM_CommandHandler(void) for 4Bytes read which for XMC implementation is not the case.
The function is a left-over from SSC5.11 implementation.
ECAT_SSC v4_0_2 is in any case targeting SSC5.12 only and the function is not called anymore. So no need to worry about its implementation.
From our perspective no need for manual changes on your side.
Kind Regards
Michael
please check the Register EEPROM Control/Status and the read-only bitfield BYTES inside reference manual:
Supported number of EEPROM read bytes
0B 4 Bytes
1B 8 Bytes
For XMC48 this bitfield always reads back 1B.
Hardware implementation is fixed to 8Bytes. This setting cannot be changed by software.
With SSC5.12 the HW_EepromReload is only getting called inside void EEPROM_CommandHandler(void) for 4Bytes read which for XMC implementation is not the case.
The function is a left-over from SSC5.11 implementation.
ECAT_SSC v4_0_2 is in any case targeting SSC5.12 only and the function is not called anymore. So no need to worry about its implementation.
From our perspective no need for manual changes on your side.
Kind Regards
Michael