Code:
// Send unlock sequence
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_UNLOCK1), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_UNLOCK2), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_UNLOCK3), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_UNLOCK4), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_SYSPCFG0, 0x01U), &spiMasterRxBuffer); // Default value
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_SYSPCFG1, 0x08U), &spiMasterRxBuffer); // [3] ERREN=1 (Enable ERR input monitor)
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WDCFG0, 0x9AU), &spiMasterRxBuffer); // [3] WWDEN=1,[2] FWDEN=0, [1] WWDTSEL=1 (aka SPI), [0] WDCYC=0 (aka WDCYC=0.1ms)
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WWDCFG0, 0x00U), &spiMasterRxBuffer); // Close window CW = (0+1)*50*0.1ms = 5ms
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WWDCFG1, 0x01U), &spiMasterRxBuffer); // Open window OW = (1+1)*50*0.1ms = 10ms
// Send lock sequence
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_LOCK1), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_LOCK2), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_LOCK3), &spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_PROTCFG,TLF_LOCK4), &spiMasterRxBuffer);
TIMEOUT_USEC_Start(60U);
// Refresh watchdog first call
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WWDSCMD, 0x00U),&spiMasterRxBuffer);
// Go to normal state
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_INITERR, 0xFFU),&spiMasterRxBuffer); // 21. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_OTFAIL, 0xFFU),&spiMasterRxBuffer); // 22. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_OTWRNSF, 0xFFU),&spiMasterRxBuffer); // 23. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_MONSF0, 0xFFU),&spiMasterRxBuffer); // 24. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_MONSF1, 0xFFU),&spiMasterRxBuffer); // 25. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_MONSF2, 0xFFU),&spiMasterRxBuffer); // 26. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_MONSF3, 0xFFU),&spiMasterRxBuffer); // 27. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_SPISF, 0xFFU),&spiMasterRxBuffer); // 28. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WKSF, 0xFFU),&spiMasterRxBuffer); // 29. Clear any error
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_DEVCTRL, 0xFAU),&spiMasterRxBuffer); // 30. Go to NORMAL and wait the State transition time ttr = 100us
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_DEVCTRLN,0x05U),&spiMasterRxBuffer); // 31. Inverted Go to NORMAL and wait the State transition time ttr = 100us
// Wait for recommended 100us for registers to set
TIMEOUT_USEC_Start(100U);
// Second service call
TLF_SPI_Exchange(TLF_ENCODE_TX_WRITE(TLF_ADDR_WWDSCMD, 0x01U),&spiMasterRxBuffer);
// registers to set
TIMEOUT_USEC_Start(100U);
// Here, Read back above protected registers and confirm if configured accurately FIXME
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_SYSFAIL , 0x00U), &spiMasterRxBuffer); // Read status
stat_SYSFAIL = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_IF , 0x00U), &spiMasterRxBuffer); // Read status
stat_IF = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_SYSSF , 0x00U), &spiMasterRxBuffer); // Read status
stat_SYSSF = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_WWDSTAT , 0x00U), &spiMasterRxBuffer); // Read status
stat_WWDSTAT = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_RSYSPCFG0, 0x00U), &spiMasterRxBuffer); // Read status
stat_RSYSPCFG0 = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_RSYSPCFG1, 0x00U), &spiMasterRxBuffer); // Read status
stat_RSYSPCFG1 = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_RWDCFG0, 0x00U), &spiMasterRxBuffer); // Read status
stat_RWDCFG0 = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_RWWDCFG0, 0x00U), &spiMasterRxBuffer); // Read status
stat_RWWDCFG0 = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_RWWDCFG1, 0x00U), &spiMasterRxBuffer); // Read status
stat_RWWDCFG1 = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
TLF_SPI_Exchange(TLF_ENCODE_TX_READ(TLF_ADDR_DEVSTAT , 0x00U), &spiMasterRxBuffer); // Read status
stat_DEVSTAT = (uint8_t) TLF_DECODE_RX(spiMasterRxBuffer);
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