Sep 01, 2020
05:32 PM
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Sep 01, 2020
05:32 PM
Can you please clarify below questions related to the Clock Safety measures for AURIX TC3xx device
Does lock monitoring of fPLLx, fSPB detects only loss of clock failure mode ? or does it also detects clock above/below the nominal frequency.
For example if my fPLLx is configured for 300Mhz and during runtime fPLLx frequency reduces to 270Mhz (10% less than actual value) will the Clock monitoring be able to detect it ?
From the reference manual looks like, it cannot ? Can you please confirm my understanding
Does lock monitoring of fPLLx, fSPB detects only loss of clock failure mode ? or does it also detects clock above/below the nominal frequency.
For example if my fPLLx is configured for 300Mhz and during runtime fPLLx frequency reduces to 270Mhz (10% less than actual value) will the Clock monitoring be able to detect it ?
From the reference manual looks like, it cannot ? Can you please confirm my understanding
- Tags:
- aurix tc3xx
- ccu
- IFX
1 Reply
Sep 03, 2020
09:07 AM
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Sep 03, 2020
09:07 AM
See also 4.2.7.2 CLOCK in the Safety Manual. The Oscillator Monitor will detect a stopped oscillator, or an oscillator running at an incorrect harmonic. The PLL will only signal an alarm on loss of lock.
So, no, it won't detect a 10% difference - but ESM[SW]:CLOCK:PLAUSIBILITY can, depending on the implementation.
So, no, it won't detect a 10% difference - but ESM[SW]:CLOCK:PLAUSIBILITY can, depending on the implementation.