System PLL configuration

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nsyed
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Do AURIX TC3xx has any in-built progressive clock switching for PLL’s ? or should this be handled in the application SW ?

By progressive clock switching, I mean switching PLL to target frequency in incremental steps, rather than a single big step.
When switching to high frequencies (300Mhz) a sudden ramp up of the PLL clock could increase power consumption leading to voltage drops on the power-supplies, this becomes critical especially during low 12V due to cold conditions.

I would like to use the automatic/built-In feature if available instead of implementing it in the application SW.
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NeMa_4793301
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There's nothing built in. The MCAL and iLLD both have examples of ramping the K2 divider up. A 50 us delay in between steps avoids power dropouts.
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nsyed
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UC_wrangler wrote:
There's nothing built in. The MCAL and iLLD both have examples of ramping the K2 divider up. A 50 us delay in between steps avoids power dropouts.


Hello,

Can you please provide the example codes which you are referring to ? I don't have access to MCAL or iLLD, from where can i get these examples ?
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MoD
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You can download the iLLDs and Demos from myicp.infineon.com in the software documentation section
I expect that you have already access to myicp.
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NeMa_4793301
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For the MCAL, see src/Mcu.c, Mcu_lSwitchToDesiredFreq().

For the iLLD, see scu/std/IfxScuCcu.h, IfxScuCcu_distributeClockInline().
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nsyed
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Thank you so much , Appreciate your help.
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