PLL N-Multiplier , K2-Divider Value

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User10891
Level 1
Level 1
Hi

Now we using fSYS Clock at 40Mhz via N-Multiplier setting as '16' , and K2-Divider setting as'2'.(Int OSC 5Mhz)

so,Is it possible change the N, K2 value as '24' and '3' ?

I think there is same fSYS value(40Mhz) , but before N-Multiplier calculation value are different '16'(80Mhz) and '24'(120Mhz).

Is there any problem if we use these value?

and one more question,

if we using like it, is the VCO RANGE also changed to 96-160Mhz?

Would you check this one?

Thanks.
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4 Replies
Elettrograffiti
Employee
Employee
Hi! You can use that N K2 configuration as soon as the VCO range is adjusted accordingly to the setup of the register VCOSEL, page 96 a 97 of the usermanual rev1.5.0.1
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User10891
Level 1
Level 1
Hi! Thanks for your support.

" The result of fR times N-factor must be within the VCO Range, the VCO Range selection has to be
adjusted accordingly"

it means that

for example, 5Mhz(Int OSC) x 23(N-Multiplier) value is must be in VCO Range.(96-120Mhz). Am I right?

Thanks.
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Elettrograffiti
Employee
Employee
Do you mean maybe 96MHZ to 160MHz? If yes, you understod it right.
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User10891
Level 1
Level 1
Sorry , it was miss typing.(120–>160Mhz)

Thanks. It was solved.
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