May 21, 2020
06:04 PM
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May 21, 2020
06:04 PM
Hello Support,
There are 3 Core CPU WDT within Aurix2G.
So, Core 0 can write to Core CPU WDT0.
Core 1 can write to Core CPU WDT1.
Core 2 can write to Core CPU WDT2.
What is the expected fail reaction when Core 0 writes to Core CPU WDT1 and hence there is an write access rule violation according to the snippet shown below?
Please provide me the Document Section where this fail action for write access rule violation is explained.
The written value is matching the expected password and all other bits. Only thing is written by alternate CPU. Then what is the failure mode of Aurix 2G?
Best Regards
There are 3 Core CPU WDT within Aurix2G.
So, Core 0 can write to Core CPU WDT0.
Core 1 can write to Core CPU WDT1.
Core 2 can write to Core CPU WDT2.
What is the expected fail reaction when Core 0 writes to Core CPU WDT1 and hence there is an write access rule violation according to the snippet shown below?
Please provide me the Document Section where this fail action for write access rule violation is explained.
The written value is matching the expected password and all other bits. Only thing is written by alternate CPU. Then what is the failure mode of Aurix 2G?
Best Regards
- Tags:
- IFX
4 Replies
May 21, 2020
06:39 PM
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May 21, 2020
06:39 PM
Bus error.
May 22, 2020
12:03 AM
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May 22, 2020
12:03 AM
Note that this is an SPB bus error - writes are posted from the SRI to SPB, which means that the error is not returned to the core. The SPB bus system will store the error in the BCU and raise an alarm.
May 22, 2020
05:17 AM
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May 22, 2020
05:17 AM
Hello Support,
Really appreciate the detailed explanation and the exact failure modes.
Attached is one snippet from User Manual about Bus Error terminology.
Can you please provide me a list of possible Bus Errors within the IC for the end-user effects other than the SPB Bus Error as explained above?
Best regards
Really appreciate the detailed explanation and the exact failure modes.
Attached is one snippet from User Manual about Bus Error terminology.
Can you please provide me a list of possible Bus Errors within the IC for the end-user effects other than the SPB Bus Error as explained above?
Best regards
Jun 02, 2020
06:41 AM
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Jun 02, 2020
06:41 AM
Hello Support,
I performed the CPU1 WDT write from CPU0.
There is no Bus Error Address stored in XBAR or no SMU ALMx bits are set.
Can you please provide me a test case using iLLD where you are able to recreate this Bus Error while write accessing CPU1 WDT from CPU0?
Best Regards
I performed the CPU1 WDT write from CPU0.
There is no Bus Error Address stored in XBAR or no SMU ALMx bits are set.
Can you please provide me a test case using iLLD where you are able to recreate this Bus Error while write accessing CPU1 WDT from CPU0?
Best Regards