What is fail action for Core CPU WDT Write from alternate CPU?

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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

There are 3 Core CPU WDT within Aurix2G.
So, Core 0 can write to Core CPU WDT0.
Core 1 can write to Core CPU WDT1.
Core 2 can write to Core CPU WDT2.

What is the expected fail reaction when Core 0 writes to Core CPU WDT1 and hence there is an write access rule violation according to the snippet shown below?
Please provide me the Document Section where this fail action for write access rule violation is explained.
The written value is matching the expected password and all other bits. Only thing is written by alternate CPU. Then what is the failure mode of Aurix 2G?
4340.attach
Best Regards
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4 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Bus error.
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Darren_Galpin
Employee
Employee
First solution authored First like received
Note that this is an SPB bus error - writes are posted from the SRI to SPB, which means that the error is not returned to the core. The SPB bus system will store the error in the BCU and raise an alarm.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
Really appreciate the detailed explanation and the exact failure modes.
Attached is one snippet from User Manual about Bus Error terminology.
Can you please provide me a list of possible Bus Errors within the IC for the end-user effects other than the SPB Bus Error as explained above?
4343.attach
Best regards
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
I performed the CPU1 WDT write from CPU0.
There is no Bus Error Address stored in XBAR or no SMU ALMx bits are set.
Can you please provide me a test case using iLLD where you are able to recreate this Bus Error while write accessing CPU1 WDT from CPU0?
Best Regards
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