Debug and CPU registers error using DAP IF

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
User18665
Level 3
Level 3
Dear All,
I try to FLASHing TC397XE chip using the DAP IF.
With DAP telegrams , I can halt main CPU (using the HARR issue). I saw, that corresponds bit are set (HARR bit in IOINFO register). Also, I can enable debug unit and unlock interface (IF_LCK bit is cleared and OEN bit is set).
Then, I can switch on SUPERVISOR MODE and I saw, that mode is set. Using the DAP, I can successfully read any CERBERUS and CPU registers. But, when I try to write the same registers, I always get BUS_WR_ERROR. By following the access rules (look at pic, yellow rect.),
I set all need permissions. ACCEN0/1 registers in all "1" too (it mean's that writing is permitted ) But, I get bus writing error any way.
By the way, I can successfully write and read RAM memory (from 0x70000000 address space). So, it seems, that IO_WRITE_WORD and IO_BLOCK_WRITE telegrams are work right. But, I can't write any registers from 0xFxxxxxxx address space.
A couldn't understand the reason: where is I'm wrong. I looking for qualified help from here.
0 Likes
6 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Do you get the same bus error with COMDATA? If so, can you post your telegrams?

The "E" registers are ENDINIT protected, so you'll either need to go through the unlock sequence - see 9.4.4 The Endinit Functions in AURIXTC3XX_um_part1_v1.5.pdf. Alternately, you could "cheat" by setting CBS_OSTATE.ENIDIS via CBS_OCNTRL=0xC0, so that all writes via Cerberus bypass the ENDINIT protection system.
0 Likes
User18665
Level 3
Level 3
UC_wrangler wrote:
Do you get the same bus error with COMDATA? If so, can you post your telegrams?

The "E" registers are ENDINIT protected, so you'll either need to go through the unlock sequence - see 9.4.4 The Endinit Functions in AURIXTC3XX_um_part1_v1.5.pdf. Alternately, you could "cheat" by setting CBS_OSTATE.ENIDIS via CBS_OCNTRL=0xC0, so that all writes via Cerberus bypass the ENDINIT protection system.



For register access I use only RW mode, instead of COMMUNICATION mode. Also, I use Clear ENDINIT and Safety ENDINIT, if it need for some registers. I saw, that ENDINIT did cleared in that cases.
0 Likes
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
alexeyPhyton wrote:
Also, I use Clear ENDINIT and Safety ENDINIT, if it need for some registers. I saw, that ENDINIT did cleared in that cases.

Wait wait the WDTCPU registers are at 0xFxxxxxxx too (e.g., SCU_WDTCPU0CON0 at 0xF0036100).

What if you write to an unrestricted register like P00_OUT (0xF003A000)? Does that also fail?
0 Likes
User18665
Level 3
Level 3
I can't write CBS_OCNTRL register too..... I got WR_BUS_ERROR too...
0 Likes
User18665
Level 3
Level 3
UC_wrangler wrote:
Wait wait the WDTCPU registers are at 0xFxxxxxxx too (e.g., SCU_WDTCPU0CON0 at 0xF0036100).

What if you write to an unrestricted register like P00_OUT (0xF003A000)? Does that also fail?


Yes. you right, sorry. I checked and I can write SCU_WDTSCON0_REG register without error. But I can't write to PC register for example....
0 Likes
User18665
Level 3
Level 3
Yes, I check and I can also successfully write P00
0 Likes