Level 4
I am looking at the DAVE 4 I2C_Master app to see the correct way to configure the system to use interrputs for TX and RX together with the FIFOs. My simple example works, but I noticed there seems to be a bug in the I2C_MASTER_TransmitHandler() function.
In line 326 there is a while that waits for the TXFIFO to become empty. This means that this interrupt routine blocks the system until all the data minus byte is transferred!
An interrupt routine must NEVER block the system!
Is this a bug, or is there no other way to solve this problem?
To measure the timing of the interrupt rountines I have added a port set/reset line at the beginning and end of the interrupt routines. This way I can measure the timing ith an oscilloscope.
In line 326 there is a while that waits for the TXFIFO to become empty. This means that this interrupt routine blocks the system until all the data minus byte is transferred!
An interrupt routine must NEVER block the system!
Is this a bug, or is there no other way to solve this problem?
To measure the timing of the interrupt rountines I have added a port set/reset line at the beginning and end of the interrupt routines. This way I can measure the timing ith an oscilloscope.
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