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Thread: TC399 Flash sequence for write pflash & dflash

  1. #11
    Advanced Advanced cwunder will become famous soon enough
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    Just to add to the comment by UC_wrangler please note in the code example that I posted, I have located the function Flash_WriteProgPage in the PSPR of CPU0.

    I am using Gnuc toolchain
    __attribute__((asection(".cpu0_psram", "a=4", "f=xwc0"))) uint8 Flash_WriteProgPage(uint64 *dst, uint64 *src, uint8 pxBusy)

  2. #12
    Beginner Beginner kfir is on a distinguished road
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    I do not know which trap , but trap table starts at:
    0x80000300

    Code:
    first_trap_table:
    0x80000300 00 A0        DEBUG     
    0x80000302 BB 00 00 E0  MOV.U     d14,0x0
    0x80000306 42 FE        ADD       d14,d15
    0x80000308 60 EE        MOV.A     a14,d14
    0x8000030A 11 DE EA ED  ADDIH.A   a14,a14,0xDEAD
    0x8000030E 1D 00 EC 05  J         call_frame_dummy (0x80000EE6)  
    0x80000312 3C 00        J         0x80000312  
    0x80000314 00 00        NOP       
    0x80000316 00 80        RFE       
    0x80000318 00 00        NOP       
    0x8000031A 00 00        NOP       
    0x8000031C 00 00        NOP       
    0x8000031E 00 00        NOP       
    0x80000320 00 A0        DEBUG     
    0x80000322 BB 00 10 E0  MOV.U     d14,0x100
    0x80000326 42 FE        ADD       d14,d15
    0x80000328 60 EE        MOV.A     a14,d14
    0x8000032A 11 DE EA ED  ADDIH.A   a14,a14,0xDEAD
    0x8000032E 1D 00 DC 05  J         call_frame_dummy (0x80000EE6)  
    0x80000332 3C 00        J         0x80000332  
    0x80000334 00 00        NOP       
    0x80000336 00 80        RFE       
    0x80000338 00 00        NOP       
    0x8000033A 00 00        NOP       
    0x8000033C 00 00        NOP       
    0x8000033E 00 00        NOP       
    0x80000340 00 A0        DEBUG     
    0x80000342 BB 00 20 E0  MOV.U     d14,0x200
    0x80000346 42 FE        ADD       d14,d15
    0x80000348 60 EE        MOV.A     a14,d14
    0x8000034A 11 DE EA ED  ADDIH.A   a14,a14,0xDEAD
    0x8000034E 1D 00 CC 05  J         call_frame_dummy (0x80000EE6)  
    0x80000352 3C 00        J         0x80000352  
    0x80000354 00 00        NOP       
    0x80000356 00 80        RFE       
    0x80000358 00 00        NOP       
    0x8000035A 00 00        NOP       
    0x8000035C 00 00        NOP       
    0x8000035E 00 00        NOP       
    0x80000360 00 A0        DEBUG     
    0x80000362 BB 00 30 E0  MOV.U     d14,0x300
    0x80000366 42 FE        ADD       d14,d15
    0x80000368 60 EE        MOV.A     a14,d14
    0x8000036A 11 DE EA ED  ADDIH.A   a14,a14,0xDEAD
    0x8000036E 1D 00 BC 05  J         call_frame_dummy (0x80000EE6)  
    0x80000372 3C 00        J         0x80000372  
    0x80000374 00 00        NOP       
    0x80000376 00 80        RFE       
    0x80000378 00 00        NOP       
    0x8000037A 00 00        NOP       
    0x8000037C 00 00        NOP       
    0x8000037E 00 00        NOP       
    0x80000380 00 A0        DEBUG     
    0x80000382 BB 00 40 E0  MOV.U     d14,0x400
    0x80000386 42 FE        ADD
    Stack of traps:
    Click image for larger version

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  3. #13
    Beginner Beginner kfir is on a distinguished road
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    I will point out that 1 page is written successfully

  4. #14
    Beginner Beginner kfir is on a distinguished road
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    Quote Originally Posted by UC_wrangler View Post
    Note that the AURIX does not support writing to PFLASH while anything is reading from the same PFLASH bank - including the CPU. If you want to write to PFLASH0, that means you either need to execute from some other PFLASH bank, or from RAM.
    So how come this works in step-by-step debug?

    moreover, I use flash bank pf0 in the firs bank but write to the second, i.e 0xA0004000
    Last edited by kfir; Apr 1st, 2020 at 11:13 AM.

  5. #15
    Advanced Advanced cwunder will become famous soon enough
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    Quote Originally Posted by kfir View Post
    So how come this works in step-by-step debug?
    A page write time of the PFlash only takes a maximum of 80us (5V) or 115us (3.3V). When single stepping the debugger it can recover when the flash is not available (for the flash operation) since I doubt you are able to press the step button faster than this.

    Quote Originally Posted by kfir View Post
    moreover, I use flash bank pf0 in the firs bank but write to the second, i.e 0xA0004000
    On the TC399 the Program Flash (16 MByte) is made up of 6 banks, the first five are 3 MBytes in size with the last bank being only 1 MByte in size.

    PF0 is is defined between 0xA0000000 -- 0xA02FFFFF. I think you are confused in the flash terminology as you are talking about flash sectors (16 KByte) not banks.

    Please provide the address address range for the code that you are executing the Flash operation on.

    As stated previously the easiest is to run from the Program Scratch Pad Ram (PSPR).
    If you want to execute the routines in PFlash to update PFlash then you cannot execute the flash command sequences in the same flash bank that you are running from.

    From the user's manual:
    Triggering an NVM operation using the command sequences takes the DMU into Command Mode. During its execution the Flash bank reports BUSY in DMU_HF_STATUS. In this mode read accesses to a Flash bank are refused with a bus error or the ready is suppressed until BUSY clears.

  6. #16
    Beginner Beginner kfir is on a distinguished road
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    Thanks @cwunder and @UC_wrangler everything is working now.

    Thanks vrey much for all the help.

  7. #17
    Beginner Beginner kfir is on a distinguished road
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    One last question.....

    Are the delays for erase different from write?

  8. #18
    Advanced Advanced cwunder will become famous soon enough
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    Quote Originally Posted by kfir View Post
    Are the delays for erase different from write?
    Yes, please consult the datasheet

    You can see the erase time per logical sector or multi-sector command can take a maximum of 500ms.
    While the program time for a page is measured in microseconds.

  9. #19
    Beginner Beginner kfir is on a distinguished road
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    Quote Originally Posted by cwunder View Post
    Yes, please consult the datasheet

    You can see the erase time per logical sector or multi-sector command can take a maximum of 500ms.
    While the program time for a page is measured in microseconds.
    I couldn't find in the documentation any reference to the different delays in in different checks of each bit in the AURIX_3XX manual, in section "Erase Logical Sector Range"

  10. #20
    Advanced Advanced cwunder will become famous soon enough
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    If you are referring to the delay for the BUSY bit to be set during the command sequence then there is no difference.

    This is defined as;
    Wait for 2*1/fFSI ns (DFlash) or 3*1/fFSI + 8*1/fSRI ns (PFlash)

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