How to avoid multiple CPU access to Safety Watchdog ENDINIT access during SMU Alarms

[User9635]

Hello Support,

For the SMU Alarm Service in Aurix 2G devices, within the ISR, user need to clear the Interrupt Request Flag.
That means SMU AEXCLR Register shall be written.
But AEXCLR register is SE protected.
SMU Alarms can be distributed across multiple cores via AGC Register settings.
That means multiple ISR from different core need to access Safety Watchdog registers because AEXCLR register is SE protected.
That is fraught with peril as already mentioned in the following post :
https://www.infineonforums.com/threads/11012-Proper-way-to-modify-CPUx_COMPAT-and-CPUx_SYSCON-Regist...
by UC_Wrangler on 16 Feb 2020

Please let me know how to clear the AEX Register Interrupt Request Flag within the ISR routine when various SMU Alarms are across different cores without violating Safety Watchdog manipulation by multiple cores.
Best Regards

[NeMa_4793301]

There is no magic bullet here - you need to find a way to avoid manipulating a single hardware resource by multiple masters simultaneously.

Here are just a few possibilities - you could implement this other ways as well:
- The CPU that gets the interrupt stores alarm information somewhere and then logs a request for a "master" CPU to clear the alarm
- Configure the SMU to cause an NMI instead of an IRQ, and code the NMI handlers so that only one CPU clears the alarms
- Create a semaphore for Safety Endinit handling and put a small timeout loop in the IRQ handler (assuming Safety Endinit critical sections will be very short)

[User9635]

Hello Support,

"- The CPU that gets the interrupt stores alarm information somewhere and then logs a request for a "master" CPU to clear the alarm"

For this item, implementation is absolutely impossible in the current architecture I suppose without violating the Safety Watchdog manipulation.
Because every ISR before returning from epilogue, it must clear the corresponding AEXCLR register.
Hence the violation.
Please let me know if you agree that there is no way to implement the first method mentioned by you without violating the other principle of muticore access to Safet Watchdog.
Best Regards

[NeMa_4793301]

Have the ISR wait for the other CPU to do it.