Aurix 2G NPCRi (i=0-3).LBM bit SET and RXSEL field

[User9635]

Hello Support,

For Aurix 2G, in the MCM_CAN module when internal loopback mode is selected via NPCRi (i=0-3).LBM=1 for a CAN Node, then RXSEL field of NPCRi (i=0-3) register is ignored or it has to set to a Port Pit?
Best Regards

[NeMa_4793301]

Internal Loop Back Mode disconnects RXD:

Internal Loop Back Mode
Internal Loop Back Mode is entered by programming bits TESTi (i=0-3).LBCK and CCCRi (i=0-3).MON to one. This
mode can be used for a “Hot Selftest”, meaning the M_CAN can be tested without affecting a running CAN system
connected to the pins TXD and RXD. In this mode pin RXD is disconnected from the M_CAN and pin TXD is held
recessive.

[User9635]

Hello Support,

I am asking about the following section from User Manual Part 2 Revision 1.4 :
40.3.1.4.1 Module internal Loop-Back Mode
Figure 587 Module Internal Loop-Back Mode

My question was not for the section "40.3.2.1.9 Test Modes".
Please let me know for the section 40.3.1.4.1 whether RXSEL value is important or not.

Best Regards

[NeMa_4793301]

Have a look at Figure 588 Module Loop-Back Mode Out. RXSEL is important for Normal operation and Loop Back Mode Out. RXSEL is not used for Internal Loop Back mode.