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Thread: XMC4200 : bit frame generation

  1. #1
    Beginner Beginner Enzo is on a distinguished road
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    XMC4200 : bit frame generation

    Hello!!!

    I'm using Infineon XMC4200 to generate in a certain output port , for example Port2 , 8 contemporary bit frames that have to be repeated cyclically for example every 1 sec.
    Every bit frame is composed by 8 bits and the bit timing has to be 20usec; therefore the transmission of the frame lasts 20usec x 8 =160 usec
    Considering that :
    Frame0 is the frame in the output P2.0 and its value is 0x00,
    Frame1 is the frame in the output P2.1 and its value is 0x01,
    and so on until Frame7 for output P2.7 value 0x07,
    we would obtain in the port2 the following signals that have to be repeated cyclically every 1 sec:

    Click image for larger version

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    How this can be achieved using an HW peripheral of the XMC4200 ?

    (Value reported for the bit frames are just an example).
    Thank you in advance for the help
    Enzo
    ?????? ?????? FrameBit.png‎  

  2. #2
    Intermediate Intermediate rst is on a distinguished road
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    Quote Originally Posted by Enzo View Post
    How this can be achieved using an HW peripheral of the XMC4200 ?
    Use few some CCUs (CCU40 && CCU80) to generate. To start multiple CCUs synchronously, use register CCUCON.

  3. #3
    Beginner Beginner Enzo is on a distinguished road
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    I think that the usage of the CCU requires SW that has to be executed in very few time. So I was wondering about some other solution.
    My idea is , define an array in memory in which the bit0 contain the value for frame0, bit 1 for frame1 and so on.....:
    Uint8 FrameTable [8] = {
    0000 0000b,
    0000 0000b,
    0000 0000b,
    0000 0000b,
    0000 0000b,
    1111 0000b,
    1100 1100b,
    1010 1010b}

    Use a CCU40 to trigger automatically the DMA transfer from the 1 first element of the table to the Port2.
    In the next cycle (20usec later), the second element will be transferred by the DMA from memory to Port2 and so on until all the 8 elements of the table are transferred (160usec in total).
    I’m not sure if the DMA can be configured to achieve this.
    Not so easy to explain , I hope it is enough clear

  4. #4
    Intermediate Intermediate rst is on a distinguished road
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    Quote Originally Posted by Enzo View Post
    Use a CCU40 to trigger automatically the DMA transfer from the 1 first element of the table to the Port2.
    In the next cycle (20usec later), the second element will be transferred by the DMA from memory to Port2 and so on until all the 8 elements of the table are transferred
    I think - it will work badly. Because transfers DMA->GPIO are carried out via internal bus, which is also used by CPU and other bus-masters. So there delays will occur due to bus occupancy, which means there will be jitter of signal edges. Thus, edges of signals will depend on bus occupancy by other bus-masters.
    Another thing - CCU wich itself generates time-characteristics of its signals. And it does it very accurately.

  5. #5
    Beginner Beginner Enzo is on a distinguished road
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    Tank you Rst for the help.....I have used in the past the CCUx to generate PWM signal but at the moment is not clear for me how to use the peripheral for this particular case....
    Anyway what I know is the output signal changes its status when the CCU timer matches the compare value and the period value, so in this case at every compare and period interrupt handler the SW has to recalculate the new compare value.
    It is an heavy load for the microcontroller, Isn't it ?

    Or perhaps I have not understand....
    :-(

  6. #6

    Infineon Employee
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    jferreira will become famous soon enough
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    Hi,

    You could give a try to the LEDTS module, https://www.infineon.com/dgdl/Infine...4b0780e33a2268. See examples in the XMCLib for XMC1200 but easily portable to XMC4200.
    Alternatively you could also use two USIC channels in quad SPI mode.

    Regards,
    Jesus
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  7. #7
    Intermediate Intermediate rst is on a distinguished road
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    Quote Originally Posted by Enzo View Post
    It is an heavy load for the microcontroller, Isn't it ?
    You can use DMA to load compare values to CCU (via shadow registers). Compare values ​​can be calculated in advance.

  8. #8
    Beginner Beginner Enzo is on a distinguished road
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    Quote Originally Posted by jferreira View Post
    Hi,

    You could give a try to the LEDTS module, https://www.infineon.com/dgdl/Infine...4b0780e33a2268. See examples in the XMCLib for XMC1200 but easily portable to XMC4200.
    Alternatively you could also use two USIC channels in quad SPI mode.

    Regards,
    Jesus
    Hello,
    The initial specifications have been a little bit changed , now each bit frame includes 9 bits and not 8 as in the picture of my first post. So that, if I have understood rightly , the LEDTS peripheral is not usable. I’m now focused on using 2 USIC channels in QUAD SPI mode.
    As first step I would run the “QSPI_EXAMPLE_XMC45” that I have rewritten exactly in the same way for XMC4200.
    Unfortunately the signals behaviour is not what I expect . I mean , when the application sends the “WRITE_ENABLE” command (0x06), it seems the ChipSelect and SLCK are activated properly but nothing happens in the IO2 and IO3 pins.About IO0 and IO1 , I do not know where they are in the XMC4200 hexagon board. I have tried with different data values , I mean different from 0x06 but the IO2 and IO3 remains always unchanged . In the picture :
    CH1 ChipSelect
    CH2 SLCK
    CH3 : IO2
    CH4 : IO3
    Thank for the help
    Click image for larger version

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  9. #9
    Beginner Beginner Enzo is on a distinguished road
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    I’m now able to transmit a data split in quad data lines writing its value in the IN07 register. Problem is now that bit timing is not guaranteed due to the delay there is in the SLCK line every 2 cycle. See the picture. So I’m wondering how to avoid this and obtain the same timing for all the bits…
    CH1 SCLK
    CH2 to CH4 IO0-IO1-IO2

    Click image for larger version

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