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Thread: IRPS54012: LDO (Page 4 ~ Channel 5 ) VOUT readout gives wrong results

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    New Member New Member Deville is on a distinguished road
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    IRPS54012: LDO (Page 4 ~ Channel 5 ) VOUT readout gives wrong results

    Hi Infineon,

    I'm trying to readout 3x IRPS54012 devices located on our custom PCB. For the Switchers all goes well ( page 0 -> page 3 ) Except for the LDO readouts I'm getting different results.

    Following is a log of all the outputs of the onboard Infineon devices made by a python script.

    Code:
    Test   1 :  Date          : Mon Feb 24 13:23:38 UTC 2020
    Test   2 :  U1 : irps54012 : VD+0.85VDC    : Page  0 : 0.8593 V ( expected: 0.8500 V )
    Test   3 :  U1 : irps54012 : VD+1.85VDC    : Page  1 : 1.8007 V ( expected: 1.8500 V )
    Test   4 :  U1 : irps54012 : VD+0.9VDC     : Page  2 : 0.8984 V ( expected: 0.9000 V )
    Test   5 :  U1 : irps54012 : VD+1.2VDC     : Page  3 : 1.1991 V ( expected: 1.2000 V )
    Test   6 :  U1 : irps54012 : VD+0.85VDC    : Page  4 : 1.6874 V ( expected: 0.8500 V )
    Test   7 :  U3 : irps54012 : VD+2.5VDC     : Page  0 : 2.5037 V ( expected: 2.5000 V )
    Test   8 :  U3 : irps54012 : VD+1.2VDC     : Page  1 : 1.2030 V ( expected: 1.2000 V )
    Test   9 :  U3 : irps54012 : VD+1.8VDC     : Page  2 : 1.7968 V ( expected: 1.8000 V )
    Test  10 :  U3 : irps54012 : VD+1.8VDC     : Page  3 : 1.8007 V ( expected: 1.8000 V )
    Test  11 :  U3 : irps54012 : VD+1.2DCL     : Page  4 : 2.4217 V ( expected: 1.2000 V )
    Test  12 :  U2 : irps54012 : VD+3.3VDC     : Page  0 : 3.3045 V ( expected: 3.3000 V )
    Test  13 :  U2 : irps54012 : VD+3.3VDC     : Page  1 : 3.3045 V ( expected: 3.3000 V )
    Test  14 :  U2 : irps54012 : VADJ          : Page  2 : 1.7968 V ( expected: 1.8000 V )
    Test  15 :  U2 : irps54012 : VD+5VDC       : Page  3 : 4.9997 V ( expected: 5.0000 V )
    Test  16 :  U2 : irps54012 : VD+3.3VDCL    : Page  4 : 6.6090 V ( expected: 3.3000 V )
    You can cleary see all the LDO's on page 4 are calculated wrongly. The real voltage on the PCB is correct.
    The mantissa for all the switchers are set to 0x18 ( reg 0x20 ) which represents a mantissa of ( 2^-8 ) while I suspect the mantissa for the LDO's should have been 0x17, which gives a mantissa of ( 2^-9 )

    The mantissa of the LDO's are set to 0x18 so the actual calculation seems done right according the LDO register settings.

    Code:
    $ sudo i2cget -y 1  0x43  0x20 
    0x18
    
    $ sudo i2cdump -y  1  0x43
    No size specified (using byte-data access)
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 04 80 17 d5 XX 00 XX XX XX XX XX XX XX XX XX XX    ????X.XXXXXXXXXX
    10: 00 XX 97 XX XX fc c3 XX XX b0 XX XX XX XX XX XX    .X?XX??XX?XXXXXX
    20: 18 da 00 XX b3 f1 c3 04 XX 08 XX XX XX XX XX XX    ??.X????X?XXXXXX
    30: XX XX XX 20 XX 28 20 XX XX 00 XX XX XX XX XX XX    XXX X( XX.XXXXXX
    40: 40 80 0d a6 73 80 d0 c0 XX XX c0 XX XX XX XX 78    @???s???XX?XXXXx
    50: 80 64 XX XX XX e0 80 XX 90 XX XX XX XX XX c0 a6    ?dXXX??X?XXXXX??
    60: 00 08 0c 80 3c 08 XX XX XX XX XX XX XX XX XX XX    .???<?XXXXXXXXXX
    70: XX XX XX XX XX XX XX XX 02 02 00 00 00 00 82 XX    XXXXXXXX??....?X
    80: XX XX XX XX XX XX XX XX 79 02 XX d9 18 25 XX XX    XXXXXXXXy?X??%XX
    90: XX XX XX XX XX XX 0a 08 22 03 04 04 XX XX XX XX    XXXXXX??"???XXXX
    a0: XX XX XX XX XX XX XX XX XX XX XX XX XX 01 01 XX    XXXXXXXXXXXXX??X
    b0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX
    c0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX
    d0: XX XX XX XX XX XX 10 XX 00 01 XX de 1a 25 XX XX    XXXXXX?X.?X??%XX
    e0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX
    f0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX
    I'm clearly missing something here. Does someone have an idea what i'm doing wrong?

    Thanks for helping me.
    Last edited by Deville; Feb 24th, 2020 at 06:09 AM.

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