Feb 12, 2020
08:48 AM
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Feb 12, 2020
08:48 AM
Hi,
I am implementing a aurix-fpga communication with the HSSL/HSCT link and after reading the documentation I would need a bit of clarification on the frame headers.
- The HSCT link has data channels A through D, but I could not find out how and when different channels are used. Is there a correspondence between the HSSL channel and HSCT channel so that HSSL channel 0 data is always used with HSCT data channel A, 1 with B... or some other specific use?
- There is a table "Mapping of HSSL to HSCT channel codes" with "HSSL channel number, special code". When is the HSSL special code used?
- Is the CRC calculated from the entire communication frame with both HSCT and HSSL headers, or just for the HSSL frame wrapped inside the HSCT frame?
- When HSSL 256 bit stream frames are sent, is the HSCT payload size 256bits with code (b101) or 288 bits code (b111)?
- Do I need to implement handshaking for the master to work, or can I test the communication with just sending for example a read command from aurix and sending back a corresponding dataframe and acknowledge with lowest link speed without configuration frames sent through the hssl link?
Kind regards,
Jhonka
I am implementing a aurix-fpga communication with the HSSL/HSCT link and after reading the documentation I would need a bit of clarification on the frame headers.
- The HSCT link has data channels A through D, but I could not find out how and when different channels are used. Is there a correspondence between the HSSL channel and HSCT channel so that HSSL channel 0 data is always used with HSCT data channel A, 1 with B... or some other specific use?
- There is a table "Mapping of HSSL to HSCT channel codes" with "HSSL channel number, special code". When is the HSSL special code used?
- Is the CRC calculated from the entire communication frame with both HSCT and HSSL headers, or just for the HSSL frame wrapped inside the HSCT frame?
- When HSSL 256 bit stream frames are sent, is the HSCT payload size 256bits with code (b101) or 288 bits code (b111)?
- Do I need to implement handshaking for the master to work, or can I test the communication with just sending for example a read command from aurix and sending back a corresponding dataframe and acknowledge with lowest link speed without configuration frames sent through the hssl link?
Kind regards,
Jhonka
- Tags:
- IFX
2 Replies
Aug 04, 2020
12:34 AM
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Aug 04, 2020
12:34 AM
Hi Jhonka,
We also try to implement aurix-fpga communication with the HSSL/HSCT link, but information is really scarce. I only found three documents by Infineon (AP32462, AP32255 and AP32365) as well as a short presentation ("AURIX™ TC2xx™ Microcontroller Training V1.0 2019"), but I still have many questions, especially regarding the implementaton of the protocol on the FPGA. The Infineon documents mainly focus on Aurix-Aurix communication and don't tell a lot about the protocol itself which would be required to implement it on other devices.
There's an IP core (logiHSSL by logicBRICKS) used in this starter kit if that's in your budget but I don't know if that helps.
In the meantime, did you have any successes or any other documents or sources which might help us?
Best regards,
Matthias
We also try to implement aurix-fpga communication with the HSSL/HSCT link, but information is really scarce. I only found three documents by Infineon (AP32462, AP32255 and AP32365) as well as a short presentation ("AURIX™ TC2xx™ Microcontroller Training V1.0 2019"), but I still have many questions, especially regarding the implementaton of the protocol on the FPGA. The Infineon documents mainly focus on Aurix-Aurix communication and don't tell a lot about the protocol itself which would be required to implement it on other devices.
There's an IP core (logiHSSL by logicBRICKS) used in this starter kit if that's in your budget but I don't know if that helps.
In the meantime, did you have any successes or any other documents or sources which might help us?
Best regards,
Matthias
Aug 06, 2020
07:33 AM
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Aug 06, 2020
07:33 AM
If you're dealing with a Xilinx FPGA, this might also help:
https://www.infineon.com/cms/en/product/promopages/AURIX_XILINX_FPGA_LINK/
https://www.infineon.com/cms/en/product/promopages/AURIX_XILINX_FPGA_LINK/