Jan 31, 2020
02:59 AM
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Jan 31, 2020
02:59 AM
Hello,
In case of TC36x we would like to confirm that CPU0 can access to CPU1 memories and CPU1 can access to CPU0 memories through SRI interconnect bus.
It is written in the documentation in Mapping of SRI Slaves to Domain 0 Slave Interfaces paragraph of AURIXTC3XX_um_part1_V1.2.0 CPU0P and CPU0S: could you give us the definition of CPU0P and CPU0S?
Is there any restriction on the type of memory CPU can access to each other?
Regards,
Jean-Marc
In case of TC36x we would like to confirm that CPU0 can access to CPU1 memories and CPU1 can access to CPU0 memories through SRI interconnect bus.
It is written in the documentation in Mapping of SRI Slaves to Domain 0 Slave Interfaces paragraph of AURIXTC3XX_um_part1_V1.2.0 CPU0P and CPU0S: could you give us the definition of CPU0P and CPU0S?
Is there any restriction on the type of memory CPU can access to each other?
Regards,
Jean-Marc
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Jan 31, 2020
04:15 AM
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Jan 31, 2020
04:15 AM
Yes, CPU0 can access to CPU1 memories and CPU1 can access to CPU0 memories through SRI interconnect bus.
Each CPUx (x = 0…1) has both an SRI Slave connection for access to its associated PFlash (labelled CPUxP in SCI tables), and an SRI Slave connection for access to its associated SRAMs, SFRs and CSFRs (labelled CPUxS in SCI tables).
Global segment for access to memory of CPU0 is 0x7, for CPU1 0x6. Please see the memory map for the location of the different memories.
Each CPUx (x = 0…1) has both an SRI Slave connection for access to its associated PFlash (labelled CPUxP in SCI tables), and an SRI Slave connection for access to its associated SRAMs, SFRs and CSFRs (labelled CPUxS in SCI tables).
Global segment for access to memory of CPU0 is 0x7, for CPU1 0x6. Please see the memory map for the location of the different memories.