Jan 22, 2020
08:25 AM
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Jan 22, 2020
08:25 AM
In my application, I need to use four TLE5012, read through SPI.
Four chips, I use 1 CLK, 1 DATA, 4 CS connections.
A single one can be used normally. But when four are used together.
When one CS line is low and the rest are high, the DATA line will be forced to LOW. In other words, when CS is high, DATA is not the high resistance I want.
Why is that?
Four chips, I use 1 CLK, 1 DATA, 4 CS connections.
A single one can be used normally. But when four are used together.
When one CS line is low and the rest are high, the DATA line will be forced to LOW. In other words, when CS is high, DATA is not the high resistance I want.
Why is that?
2 Replies
Jan 22, 2020
10:51 PM
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Jan 22, 2020
10:51 PM
The SSC interface has the defaut push-pull configuration. To use the open-drain configuration the bit SSC_OD has to be used.See sections 3.7/3.8 in the user's manual.
Feb 02, 2020
03:42 AM
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Feb 02, 2020
03:42 AM
Here with me。No matter what mode DATA is set to,As long as CSQ is not selected (high), DATA will be forced low.