Channel turn on/off delay measurement

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User17952
Level 3
Level 3
Hi,
In the chapter of BDRV(27.3.7), I saw that TLE987x can measure the delay between intended external MOS activation and actual turn on .I don't know how to do it , and is there any demo code to implement it?
Best!
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1 Solution
Fiz
Moderator
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First like received 50 replies posted 25 replies posted
Hi Liang Xiao,

if you look into into the BDRV.CTRL2 register you will find all functionalities to work with this feature.
You will need decide which time you want to measure (turn-on/off) by setting:
BDRV.CTRL2->DLY_DIAG_DIRSEL
Then you need to decide which MOSFET you want so supervise by setting
BDRV.CTRL2->DLY_DIAG_CHSEL
If the BDRV.CTRL2->DLY_STS flag is set to you can read back the measured timing in BDRV.CTRL2->DLY_DIAG_TIM
Then you will need to set BDRV.CTRL2->DLY_DIAG_SCLR to clear the Diag timer valid flag.
3921.attach
Best,
Fiz

View solution in original post

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5 Replies
Fiz
Moderator
Moderator
Moderator
First like received 50 replies posted 25 replies posted
Hi Liang Xiao,

if you look into into the BDRV.CTRL2 register you will find all functionalities to work with this feature.
You will need decide which time you want to measure (turn-on/off) by setting:
BDRV.CTRL2->DLY_DIAG_DIRSEL
Then you need to decide which MOSFET you want so supervise by setting
BDRV.CTRL2->DLY_DIAG_CHSEL
If the BDRV.CTRL2->DLY_STS flag is set to you can read back the measured timing in BDRV.CTRL2->DLY_DIAG_TIM
Then you will need to set BDRV.CTRL2->DLY_DIAG_SCLR to clear the Diag timer valid flag.
3921.attach
Best,
Fiz
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danilou
Level 1
Level 1
First like given First reply posted Welcome!

Hello,

I'm using this feature(Switch-On / Off Delay Time Measurement*) to measure the time-on/off of FETS .

Unffortunatly I have noticed some issues with BDRV.CTRL2->DLY_DIAG_TIM readings. Running several times the reported value is floating (+/-350ns). I checked on Oscilocope and that variation is not visivel (Only 75ns variation).

 

To measure the time delay between On-Off and Off-On, I do the following:

 

1st: Activate and set the PWM according the FETs I want to test;

2nd: Wait a pwm cycle (just to ensure that pwm in already set);

3rd:configure the BDRV->CTRL2.bit.DLY_DIAG_DIRSEL

4rd: configure the BDRV->CTRL2.bit.DLY_DIAG_CHSEL 

5rd: clear the flag BDRV->CTRL2.bit.DLY_DIAG_SCLR

6rd: Wait for BDRV.CTRL2->DLY_STS to be ready

7rd: Read value in: BDRV.CTRL2->DLY_DIAG_TIM.

Problem: BDRV.CTRL2->DLY_DIAG_TIM returns variation values for same pwm configuration, but when we check in osciloscope the

In osciloscope we are measuring the time between the fall/edge between Drain Source.

Am I measuring in the wrong point in osciloscope?

Increase the DSMONVTH could improve the measurement?

How is the internal switch of the start timer(BDRV.CTRL2->DLY_DIAG_TIM) set?

 

*https://www.infineon.com/dgdl/Infineon-AppNote-TLE986x-TLE987x-FAQ-Application-Hints_3-ApplicationNo... --> Chapter 9

 

 

Thank you in advance.

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RupakC
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100 solutions authored 250 sign-ins 25 likes received

Hello @danilou 

As already mentioned, DLY_DIAG_TIM holds the driver delay value. 

Please have a look at page 30 of the following document:

https://www.infineon.com/dgdl/Infineon-AppNote-TLE986x-TLE987x-FAQ-Application-Hints_3-ApplicationNo...

DLY_DIAG_TIM is the delay timer used for the delay measurement. It is started by the rising edge of the CCU6 signal CCU6_CHx and stopped by the falling edge of the drain source comparator.

So in order to check this delay in hardware, you have to probe the correct pins (delay will be from PWM rise/fall to Vds_comp fall/rise) . Rise to fall time of the Drain to Source Voltage does not relate to the delay that the register  DLY_DIAG_TIM holds. 

Also, please follow the instructions as mentioned by @Fiz  in correct order.  After reading the value of  BDRV.CTRL2->DLY_DIAG_TIM, you need to  set BDRV.CTRL2->DLY_DIAG_SCLR to clear the Diag timer valid flag.

Regards

RupakC
danilou
Level 1
Level 1
First like given First reply posted Welcome!

Hello RupakC,

Thank you.

I just changed the order and placed the clear of timer BDRV.CTRL2->DLY_DIAG_SCLR after the reading of  BDRV.CTRL2->DLY_DIAG_TIM  and values reported are wrong.

I found a note in datasheet page 857 : (https://www.infineon.com/dgdl/Infineon-TLE987x-UserManual-v01_60-EN.pdf?fileId=5546d4624e24005f014e5...) . May you please clarify why to clear the Diag needs to be reset after measurement?

Related to the measuring in HW:

There is a pinout available for the VDS_COMP ("unfiltered VDS comparator outputs" )?

Please clarify if the treshold defined in CFG_CTRL3_DSMONVTH has impact in the TimeOn/Off?

We have the DRV_CCP_DIS disabled

danilou_0-1665751418484.png

Thank you

 

 

 

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RupakC
Moderator
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100 solutions authored 250 sign-ins 25 likes received

Hello @danilou 

  1. What is the value of TIM register? Is it showing some junk value? Is the BDRV.CTRL2->DLY_STS flag SET or Reset when you are reading back the measured time ?
  2. In page 857 it is mentioned that the power diag timer valid flag must be cleared to start a measurement. When measurement finishes, the register reads 1. Resetting of  this DLY_Diag_STS initiates a measurement.
  3. You may look into figure 17 of page 30 of the following document:
    https://www.infineon.com/dgdl/Infineon-AppNote-TLE986x-TLE987x-FAQ-Application-Hints_3-ApplicationNo...
    When Vds_comp goes low, the Voltage across SHx pin (Source High Side FET) goes high. Hence you may measure the voltage VSH as a test point for Vds_comp
  1. The bit field CTRL3.DSMONVTH defines the threshold for the DS-monitoring to recognize an over-current condition in one of the MOSFETs. The DSMONVTH value defines a voltage across the drain-source path of a voltage, the required current flowing through the MOSFET needs to be calculated based on the RDS_ON value of the MOSFET. So, this bit is related to overcurrent detection and will not affect normal time on/off.

Regards

RupakC
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