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Thread: XMC4800 Sync_Latch_Config Register

  1. #1
    Beginner Beginner Max_Rock is on a distinguished road
    Join Date
    Mar 2013

    XMC4800 Sync_Latch_Config Register

    I am currently setting the EtherCAT EEPROM Configuration Area.
    The registers PDI_Control (0x80) and PDI_Config (0x81) are fixed by hardware.
    Register ESC_Config and DC_Pulse_Len change from the reset value to value from the EEPROM.
    Only the register Sync_Latch_Config always remains at 0xEE (reset value).
    I have seen this synonymous with the Osci that the reset value is active and not the value from the EEPROM.

    Now the question, am I still doing something wrong or is there a bug in the ASIC?

    I use the XMC4800 Relax Kit EtherCat with DAVE 4.4.2 and work with the demo project ETHCAT_SSC_XMC48.
    The system also comes in OP mode in my TWINCAT system.

    Greeting Max_Rock

  2. #2
    New Member New Member
    Infineon Employee
    Infineon Employee
    MichaelIFX is on a distinguished road
    Join Date
    Mar 2016
    Register 0xEE is remaining as a relict from the original BECKHOFF peripheral implementation.
    Inside XMC the LATCH/SYNC are internally remaining always enabled and you just decide by internal internconnection if you like to use or not.
    Therefore modifying this register is not needed.
    However for routing them to the pin of your choice and type selection (Push-Pull, Open Drain,...) the setting has to be done inside the IOCR bitfield of the respective XMC-pin inside your implementation.
    See also side note 1), 2) and 3) inside reference manual description of Sync_Latch_Config.

    Instead of manual register settings inside IOCR done by yourself, you can simply add a DIGITAL_IO-APP to your application, route the sync_out_0/sync_out_1 output of ECAT_APP to the DIGITAL_IO-App.
    Finally you select the driver-type/strength and pin as you wish and the IOCR-register setting will be applied by DAVE after code generation according to your settings.

    Please note: The connection of sync_out_0/sync_out_1 to INT_SYNC1 and INT_SYNC0 APP in parallel should in any case remain!
    Do not remove it when connecting the signals also(!) to the digital IO.
    Last edited by MichaelIFX; Dec 4th, 2019 at 04:54 AM.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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