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Apr 26, 2012
08:05 AM
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Apr 26, 2012
08:05 AM
We have an internal collection of user manual issues. Issues means things that aren't clear to us (from descriptions in the manual) or plain wrong.
I thought it might be convenient (for µC users as well as developers) if all such findings are collected in a single place. Just post the µC user manual issues you found therein:
I will try to keep a list of all posted issues up to date in this first post of the thread.
XC878 UM 1.1
- (Section 7.3.4) The PLLBYP bit is write protected, this is not documented in the OSC_CON register description
- (Section 5.6.3) IRCON2 lists bit CANSRC3 at bit 3, all other sources place it at bit 4
- (Table 16-5) Everything is plain wrong, e.g. PANCTR is listed at address 0x01C4, but the correct address is 0x0071, I haven't found a single correct address or offset in that table
- (Table 4-5) Lists FEAH as FEAL
- (Section 4.9) FCS.FTOV bit mentioned in section 4.4 does not exist
- (Figure 5-6) NMISR is spelled NMIISR
- (Section 9.1) The warning period 30H should be 3000H
I thought it might be convenient (for µC users as well as developers) if all such findings are collected in a single place. Just post the µC user manual issues you found therein:
I will try to keep a list of all posted issues up to date in this first post of the thread.
XC878 UM 1.1
- (Section 7.3.4) The PLLBYP bit is write protected, this is not documented in the OSC_CON register description
- (Section 5.6.3) IRCON2 lists bit CANSRC3 at bit 3, all other sources place it at bit 4
- (Table 16-5) Everything is plain wrong, e.g. PANCTR is listed at address 0x01C4, but the correct address is 0x0071, I haven't found a single correct address or offset in that table
- (Table 4-5) Lists FEAH as FEAL
- (Section 4.9) FCS.FTOV bit mentioned in section 4.4 does not exist
- (Figure 5-6) NMISR is spelled NMIISR
- (Section 9.1) The warning period 30H should be 3000H
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XC800
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May 04, 2012
02:58 AM
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May 04, 2012
02:58 AM
Added XC878 UM 1.1:
- (Section 4.9) FCS.FTOV bit mentioned in section 4.4 is not described
- (Table 2-1) MOVC @(DPTR++),A and TRAP have the same op-code 0xA5
- (Section 4.9) FCS.FTOV bit mentioned in section 4.4 is not described
- (Table 2-1) MOVC @(DPTR++),A and TRAP have the same op-code 0xA5
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May 11, 2012
05:23 AM
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May 11, 2012
05:23 AM
kamikaze wrote:As it turns out 0xA5 is the only reserved op-code in the 8052 standard. EO.TRAP_EN can be used on the XC878 to set what the op-code actually does.
Added XC878 UM 1.1:
- (Section 4.9) FCS.FTOV bit mentioned in section 4.4 is not described
- (Table 2-1) MOVC @(DPTR++),A and TRAP have the same op-code 0xA5
The bit FCS.FTOV doesn't seem to exist at all. At least not in the FCS register.
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May 14, 2012
12:30 AM
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May 14, 2012
12:30 AM
Thanks a lot for this list, it is much appreciated. We are looking into the issues and updating the UM accordingly.
And yes, as you mentioned, EO.TRAP_EN is used to select the instruction executed by op-code 0xA5.
And yes, as you mentioned, EO.TRAP_EN is used to select the instruction executed by op-code 0xA5.
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May 15, 2012
02:59 PM
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May 15, 2012
02:59 PM
Ah, thanks a lot. Is there an update schedule?
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Jun 19, 2012
02:47 AM
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Jun 19, 2012
02:47 AM
Added:
XC878 UM 1.1
- (Figure 5-6) NMISR is spelled NMIISR
XC878 UM 1.1
- (Figure 5-6) NMISR is spelled NMIISR
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Jun 26, 2012
01:32 AM
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Jun 26, 2012
01:32 AM
Added:
XC878 UM 1.1
- (Section 9.1) 30H should be 3000H
XC878 UM 1.1
- (Section 9.1) 30H should be 3000H