Nov 05, 2019
02:34 AM
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Nov 05, 2019
02:34 AM
Hi AURIX Community,
how is the CRC calculated with the DMA, for data and addresses?
Thanks!
Best regards
Christine
#8042000 19724
how is the CRC calculated with the DMA, for data and addresses?
Thanks!
Best regards
Christine
#8042000 19724
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- IFX
7 Replies
Nov 05, 2019
07:13 AM
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Nov 05, 2019
07:13 AM
Hi Christine,
The transaction control set of a DMA channel includes functionality to support
the calculation of Cyclic Redundancy Checker (CRC) checksums for source and
destination addresses and read data to support enhanced data integrity checking.
The way the CRC32 is calculated is described below with examples.
The initial values of RDCRC/SDCRC should be initialized with appropriate initial value (e.g. 0x00000000)
For instance, let's say the configuration before starting is,
0x70001F14 :SADR
0x0000000 :SHADR
0x70001BF4 :DADR
0x0000000 :SDCRC
0x0000000 :RDCRC
with 32bit, and 2 move transfer. Read data is first 0xDEADBEEF, second is 0xC0CAC01A (located in 0x70001F14 and 0x70001F18 ),
And the configuration after finished is:
0x70001F1C :SADR
0x0000000 :SHADR
0x70001BFC:DADR
0x38743952 :SDCRC
0x0660F846 :RDCRC
Then the CRC for read data is calculated by (1st read data, 2nd ,... last read data)
In this case, the expected CRC for 0xDEADBEEFC0CAC01A is 0x0660F846, which is the result of the RDCRC.
The CRC for SDCRC (Source Destination CRC) is calculated by (1st Source Address, 1st Destination Address, 2nd Source,... Last Destination Address)
In this case, the expected CRC for 0x70001F1470001BF470001F1870001BF8 is 0x38743952 , which is the result of the SDCRC.
Best regards
Mr. AURIX™
The transaction control set of a DMA channel includes functionality to support
the calculation of Cyclic Redundancy Checker (CRC) checksums for source and
destination addresses and read data to support enhanced data integrity checking.
The way the CRC32 is calculated is described below with examples.
The initial values of RDCRC/SDCRC should be initialized with appropriate initial value (e.g. 0x00000000)
For instance, let's say the configuration before starting is,
0x70001F14 :SADR
0x0000000 :SHADR
0x70001BF4 :DADR
0x0000000 :SDCRC
0x0000000 :RDCRC
with 32bit, and 2 move transfer. Read data is first 0xDEADBEEF, second is 0xC0CAC01A (located in 0x70001F14 and 0x70001F18 ),
And the configuration after finished is:
0x70001F1C :SADR
0x0000000 :SHADR
0x70001BFC:DADR
0x38743952 :SDCRC
0x0660F846 :RDCRC
Then the CRC for read data is calculated by (1st read data, 2nd ,... last read data)
In this case, the expected CRC for 0xDEADBEEFC0CAC01A is 0x0660F846, which is the result of the RDCRC.
The CRC for SDCRC (Source Destination CRC) is calculated by (1st Source Address, 1st Destination Address, 2nd Source,... Last Destination Address)
In this case, the expected CRC for 0x70001F1470001BF470001F1870001BF8 is 0x38743952 , which is the result of the SDCRC.
Best regards
Mr. AURIX™
Apr 02, 2020
08:03 PM
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Apr 02, 2020
08:03 PM
Hello Support,
Will the expected DMA Address CRC value using SDCRC register be same even for Aurix 2G assuming same addresses and data as in the previous reply?
Best Regards
Will the expected DMA Address CRC value using SDCRC register be same even for Aurix 2G assuming same addresses and data as in the previous reply?
Best Regards
Apr 03, 2020
04:59 AM
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Apr 03, 2020
04:59 AM
The CRC algorithm is the same between TC2xx and TC3xx. It also matches the CRC32 instruction.
Apr 03, 2020
02:54 PM
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Apr 03, 2020
02:54 PM
Hello Support,
In the Aurix 2G User manual Part 1 Revision 1.4, there is the following section :
18.3.5.1.1 DMA Address Checksum
It mentions something about final SDCRC register contents based on cached address and so on.
I am unable to understand the real meaning of this paragraph.
1> Please can you elaborate somewhat more about this paragraph.
2> Also, can you please point me to a similar/corresponding info for Aurix 1G User Manual -- take for example TC297 User Manual Revision 1.3
Best Regards
In the Aurix 2G User manual Part 1 Revision 1.4, there is the following section :
18.3.5.1.1 DMA Address Checksum
It mentions something about final SDCRC register contents based on cached address and so on.
I am unable to understand the real meaning of this paragraph.
1> Please can you elaborate somewhat more about this paragraph.
2> Also, can you please point me to a similar/corresponding info for Aurix 1G User Manual -- take for example TC297 User Manual Revision 1.3
Best Regards
Apr 04, 2020
11:15 AM
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Apr 04, 2020
11:15 AM
This is just documenting a restriction shared with the TC2xx: see DMA_TC.043 in the TC2xx Errata Sheet. It's a bit clearer in the erratum text:
There are many other restrictions on using non-cached memory only with linked lists, conditional DMA, etc. Stick with the non-cached addresses and you won't have to worry about it.
DMA_TC.043 DMA Write Move Data Corruption for non 32-byte Aligned Cacheable Source Address
If the DMA channel TCS selects a 256-bit channel data width and a non 32-byte aligned source address then the beat order of the DMA write move will be different for DMA read moves to cacheable (segments 8 and 9) and non-cacheable (segments A and B) source addresses. The effect is data corruption for accesses to cacheable addresses.
Workarounds
1. Use 32-byte aligned source addresses for DMA read move to cacheable addresses (segments 8 and 9).
2. Use non-cacheable source addresses (segments A and B).
There are many other restrictions on using non-cached memory only with linked lists, conditional DMA, etc. Stick with the non-cached addresses and you won't have to worry about it.
Apr 04, 2020
03:48 PM
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Apr 04, 2020
03:48 PM
Hello Support,
In the Aurix 2G Part 1 User Manual Revision 1.4,
I find the following section regarding DMA Move Engine Read Buffer of 256-Bit [BTR4 Access] similar to Program Line Buffer [PLB] :
18.3.5.1 ME Read Buffer
Can you please tell me whether similar 256-Bit Read Buffer is there in TC297 [Aurix 1G] for DMA Move Engine?
I couldn't find any information within TC297 User Manual Revision 1.3
Please let me know.
Best Regards
In the Aurix 2G Part 1 User Manual Revision 1.4,
I find the following section regarding DMA Move Engine Read Buffer of 256-Bit [BTR4 Access] similar to Program Line Buffer [PLB] :
18.3.5.1 ME Read Buffer
Can you please tell me whether similar 256-Bit Read Buffer is there in TC297 [Aurix 1G] for DMA Move Engine?
I couldn't find any information within TC297 User Manual Revision 1.3
Please let me know.
Best Regards
Apr 05, 2020
11:25 AM
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Apr 05, 2020
11:25 AM
Yes, the TC2xx has a 256-bit read buffer too. See DMA Read Buffer on page 1454 of tc29xB_um_v1.3.pdf.