Oct 28, 2019
05:46 AM
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Oct 28, 2019
05:46 AM
Hi all,
Does AURIX have a cache coherency mechanism in hardware that ensures cache coherency between different core caches?
Thank you and best regards
Lucas
#8042000 12431
Does AURIX have a cache coherency mechanism in hardware that ensures cache coherency between different core caches?
Thank you and best regards
Lucas
#8042000 12431
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- IFX
1 Reply
Oct 28, 2019
10:06 AM
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Oct 28, 2019
10:06 AM
Hi Lucas,
No, this is not covered automatically in hardware. However each memory section can be accessed as well using an uncached address (therefore same physical memory is adressed but cache is bypassed).
Also there are special instructions to ensure a proper cache write back: CACHEI and CACHEA instructions.
Please refer to the TriCore Architecture Manual for a detailed description.
Best regards
Christine
No, this is not covered automatically in hardware. However each memory section can be accessed as well using an uncached address (therefore same physical memory is adressed but cache is bypassed).
Also there are special instructions to ensure a proper cache write back: CACHEI and CACHEA instructions.
Please refer to the TriCore Architecture Manual for a detailed description.
Best regards
Christine